diff options
| author | WlodekM <[email protected]> | 2025-04-04 10:38:16 +0300 |
|---|---|---|
| committer | WlodekM <[email protected]> | 2025-04-04 10:38:16 +0300 |
| commit | 562e6237bb58919d800f431cb38de1784efbbe98 (patch) | |
| tree | af9e7e1b3271a17df26079d2b709c130f0cacc3b | |
| parent | e2568226af4af2d3b27e9e1a775e7244c5ef7191 (diff) | |
try to test,,, and fail
| -rw-r--r-- | 6502_functional_test.lst | 14360 | ||||
| -rw-r--r-- | 65c02.ts | 4 | ||||
| -rw-r--r-- | README.md | 6 | ||||
| -rw-r--r-- | eater.ts | 13 | ||||
| -rw-r--r-- | functional-test.s | 6109 | ||||
| -rw-r--r-- | runtime.ts | 35 | ||||
| -rw-r--r-- | thing.s | 2 |
7 files changed, 20519 insertions, 10 deletions
diff --git a/6502_functional_test.lst b/6502_functional_test.lst new file mode 100644 index 0000000..d178888 --- /dev/null +++ b/6502_functional_test.lst @@ -0,0 +1,14360 @@ +AS65 Assembler for R6502 [1.42]. Copyright 1994-2007, Frank A. Kingswood Page 1 +---------------------------------------------------- 6502_functional_test.a65 ---------------------------------------------------- + +6104 lines read, no errors in pass 1. + ; + ; 6 5 0 2 F U N C T I O N A L T E S T + ; + ; Copyright (C) 2012-2015 Klaus Dormann + ; + ; This program is free software: you can redistribute it and/or modify + ; it under the terms of the GNU General Public License as published by + ; the Free Software Foundation, either version 3 of the License, or + ; (at your option) any later version. + ; + ; This program is distributed in the hope that it will be useful, + ; but WITHOUT ANY WARRANTY; without even the implied warranty of + ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + ; GNU General Public License for more details. + ; + ; You should have received a copy of the GNU General Public License + ; along with this program. If not, see <http://www.gnu.org/licenses/>. + + + ; This program is designed to test all opcodes of a 6502 emulator using all + ; addressing modes with focus on propper setting of the processor status + ; register bits. + ; + ; version 04-dec-2017 + ; contact info at http://2m5.de or email [email protected] + ; + ; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/ + ; command line switches: -l -m -s2 -w -h0 + ; | | | | no page headers in listing + ; | | | wide listing (133 char/col) + ; | | write intel hex file instead of binary + ; | expand macros in listing + ; generate pass2 listing + ; + ; No IO - should be run from a monitor with access to registers. + ; To run load intel hex image with a load command, than alter PC to 400 hex + ; (code_segment) and enter a go command. + ; Loop on program counter determines error or successful completion of test. + ; Check listing for relevant traps (jump/branch *). + ; Please note that in early tests some instructions will have to be used before + ; they are actually tested! + ; + ; RESET, NMI or IRQ should not occur and will be trapped if vectors are enabled. + ; Tests documented behavior of the original NMOS 6502 only! No unofficial + ; opcodes. Additional opcodes of newer versions of the CPU (65C02, 65816) will + ; not be tested. Decimal ops will only be tested with valid BCD operands and + ; N V Z flags will be ignored. + ; + ; Debugging hints: + ; Most of the code is written sequentially. if you hit a trap, check the + ; immediately preceeding code for the instruction to be tested. Results are + ; tested first, flags are checked second by pushing them onto the stack and + ; pulling them to the accumulator after the result was checked. The "real" + ; flags are no longer valid for the tested instruction at this time! + ; If the tested instruction was indexed, the relevant index (X or Y) must + ; also be checked. Opposed to the flags, X and Y registers are still valid. + ; + ; versions: + ; 28-jul-2012 1st version distributed for testing + ; 29-jul-2012 fixed references to location 0, now #0 + ; added license - GPLv3 + ; 30-jul-2012 added configuration options + ; 01-aug-2012 added trap macro to allow user to change error handling + ; 01-dec-2012 fixed trap in branch field must be a branch + ; 02-mar-2013 fixed PLA flags not tested + ; 19-jul-2013 allowed ROM vectors to be loaded when load_data_direct = 0 + ; added test sequence check to detect if tests jump their fence + ; 23-jul-2013 added RAM integrity check option + ; 16-aug-2013 added error report to standard output option + ; 13-dec-2014 added binary/decimal opcode table switch test + ; 14-dec-2014 improved relative address test + ; 23-aug-2015 added option to disable self modifying tests + ; 24-aug-2015 all self modifying immediate opcodes now execute in data RAM + ; added small branch offset pretest + ; 21-oct-2015 added option to disable decimal mode ADC & SBC tests + ; 04-dec-2017 fixed BRK only tested with interrupts enabled + ; added option to skip the remainder of a failing test + ; in report.i65 + + + ; C O N F I G U R A T I O N + + ;ROM_vectors writable (0=no, 1=yes) + ;if ROM vectors can not be used interrupts will not be trapped + ;as a consequence BRK can not be tested but will be emulated to test RTI +0001 = ROM_vectors = 1 + + ;load_data_direct (0=move from code segment, 1=load directly) + ;loading directly is preferred but may not be supported by your platform + ;0 produces only consecutive object code, 1 is not suitable for a binary image +0001 = load_data_direct = 1 + + ;I_flag behavior (0=force enabled, 1=force disabled, 2=prohibit change, 3=allow + ;change) 2 requires extra code and is not recommended. SEI & CLI can only be + ;tested if you allow changing the interrupt status (I_flag = 3) +0003 = I_flag = 3 + + ;configure memory - try to stay away from memory used by the system + ;zero_page memory start address, $50 (80) consecutive Bytes required + ; add 2 if I_flag = 2 +000a = zero_page = $a + + ;data_segment memory start address, $6A (106) consecutive Bytes required +0200 = data_segment = $200 + if (data_segment & $ff) != 0 + ERROR ERROR ERROR low byte of data_segment MUST be $00 !! + endif + + ;code_segment memory start address, 13kB of consecutive space required + ; add 2.5 kB if I_flag = 2 +0400 = code_segment = $400 + + ;self modifying code may be disabled to allow running in ROM + ;0=part of the code is self modifying and must reside in RAM + ;1=tests disabled: branch range +0000 = disable_selfmod = 0 + + ;report errors through I/O channel (0=use standard self trap loops, 1=include + ;report.i65 as I/O channel, add 3.5 kB) +0000 = report = 0 + + ;RAM integrity test option. Checks for undesired RAM writes. + ;set lowest non RAM or RAM mirror address page (-1=disable, 0=64k, $40=16k) + ;leave disabled if a monitor, OS or background interrupt is allowed to alter RAM +ffff = ram_top = -1 + + ;disable test decimal mode ADC & SBC, 0=enable, 1=disable, + ;2=disable including decimal flag in processor status +0000 = disable_decimal = 0 + + noopt ;do not take shortcuts + + ;macros for error & success traps to allow user modification + ;example: + ;trap macro + ; jsr my_error_handler + ; endm + ;trap_eq macro + ; bne skip\? + ; trap ;failed equal (zero) + ;skip\? + ; endm + ; + ; my_error_handler should pop the calling address from the stack and report it. + ; putting larger portions of code (more than 3 bytes) inside the trap macro + ; may lead to branch range problems for some tests. + if report = 0 + trap macro + jmp * ;failed anyway + endm + trap_eq macro + beq * ;failed equal (zero) + endm + trap_ne macro + bne * ;failed not equal (non zero) + endm + trap_cs macro + bcs * ;failed carry set + endm + trap_cc macro + bcc * ;failed carry clear + endm + trap_mi macro + bmi * ;failed minus (bit 7 set) + endm + trap_pl macro + bpl * ;failed plus (bit 7 clear) + endm + trap_vs macro + bvs * ;failed overflow set + endm + trap_vc macro + bvc * ;failed overflow clear + endm + ; please observe that during the test the stack gets invalidated + ; therefore a RTS inside the success macro is not possible + success macro + jmp * ;test passed, no errors + endm + endif + if report = 1 + trap macro + jsr report_error + endm + trap_eq macro + bne skip\? + trap ;failed equal (zero) + skip\? + endm + trap_ne macro + beq skip\? + trap ;failed not equal (non zero) + skip\? + endm + trap_cs macro + bcc skip\? + trap ;failed carry set + skip\? + endm + trap_cc macro + bcs skip\? + trap ;failed carry clear + skip\? + endm + trap_mi macro + bpl skip\? + trap ;failed minus (bit 7 set) + skip\? + endm + trap_pl macro + bmi skip\? + trap ;failed plus (bit 7 clear) + skip\? + endm + trap_vs macro + bvc skip\? + trap ;failed overflow set + skip\? + endm + trap_vc macro + bvs skip\? + trap ;failed overflow clear + skip\? + endm + ; please observe that during the test the stack gets invalidated + ; therefore a RTS inside the success macro is not possible + success macro + jsr report_success + endm + endif + + +0001 = carry equ %00000001 ;flag bits in status +0002 = zero equ %00000010 +0004 = intdis equ %00000100 +0008 = decmode equ %00001000 +0010 = break equ %00010000 +0020 = reserv equ %00100000 +0040 = overfl equ %01000000 +0080 = minus equ %10000000 + +0001 = fc equ carry +0002 = fz equ zero +0003 = fzc equ carry+zero +0040 = fv equ overfl +0042 = fvz equ overfl+zero +0080 = fn equ minus +0081 = fnc equ minus+carry +0082 = fnz equ minus+zero +0083 = fnzc equ minus+zero+carry +00c0 = fnv equ minus+overfl + +0030 = fao equ break+reserv ;bits always on after PHP, BRK +0034 = fai equ fao+intdis ;+ forced interrupt disable +0038 = faod equ fao+decmode ;+ ignore decimal +003c = faid equ fai+decmode ;+ ignore decimal +00ff = m8 equ $ff ;8 bit mask +00fb = m8i equ $ff&~intdis ;8 bit mask - interrupt disable + + ;macros to allow masking of status bits. + ;masking test of decimal bit + ;masking of interrupt enable/disable on load and compare + ;masking of always on bits after PHP or BRK (unused & break) on compare + if disable_decimal < 2 + if I_flag = 0 + load_flag macro + lda #\1&m8i ;force enable interrupts (mask I) + endm + cmp_flag macro + cmp #(\1|fao)&m8i ;I_flag is always enabled + always on bits + endm + eor_flag macro + eor #(\1&m8i|fao) ;mask I, invert expected flags + always on bits + endm + endif + if I_flag = 1 + load_flag macro + lda #\1|intdis ;force disable interrupts + endm + cmp_flag macro + cmp #(\1|fai)&m8 ;I_flag is always disabled + always on bits + endm + eor_flag macro + eor #(\1|fai) ;invert expected flags + always on bits + I + endm + endif + if I_flag = 2 + load_flag macro + lda #\1 + ora flag_I_on ;restore I-flag + and flag_I_off + endm + cmp_flag macro + eor flag_I_on ;I_flag is never changed + cmp #(\1|fao)&m8i ;expected flags + always on bits, mask I + endm + eor_flag macro + eor flag_I_on ;I_flag is never changed + eor #(\1&m8i|fao) ;mask I, invert expected flags + always on bits + endm + endif + if I_flag = 3 + load_flag macro + lda #\1 ;allow test to change I-flag (no mask) + endm + cmp_flag macro + cmp #(\1|fao)&m8 ;expected flags + always on bits + endm + eor_flag macro + eor #\1|fao ;invert expected flags + always on bits + endm + endif + else + if I_flag = 0 + load_flag macro + lda #\1&m8i ;force enable interrupts (mask I) + endm + cmp_flag macro + ora #decmode ;ignore decimal mode bit + cmp #(\1|faod)&m8i ;I_flag is always enabled + always on bits + endm + eor_flag macro + ora #decmode ;ignore decimal mode bit + eor #(\1&m8i|faod) ;mask I, invert expected flags + always on bits + endm + endif + if I_flag = 1 + load_flag macro + lda #\1|intdis ;force disable interrupts + endm + cmp_flag macro + ora #decmode ;ignore decimal mode bit + cmp #(\1|faid)&m8 ;I_flag is always disabled + always on bits + endm + eor_flag macro + ora #decmode ;ignore decimal mode bit + eor #(\1|faid) ;invert expected flags + always on bits + I + endm + endif + if I_flag = 2 + load_flag macro + lda #\1 + ora flag_I_on ;restore I-flag + and flag_I_off + endm + cmp_flag macro + eor flag_I_on ;I_flag is never changed + ora #decmode ;ignore decimal mode bit + cmp #(\1|faod)&m8i ;expected flags + always on bits, mask I + endm + eor_flag macro + eor flag_I_on ;I_flag is never changed + ora #decmode ;ignore decimal mode bit + eor #(\1&m8i|faod) ;mask I, invert expected flags + always on bits + endm + endif + if I_flag = 3 + load_flag macro + lda #\1 ;allow test to change I-flag (no mask) + endm + cmp_flag macro + ora #decmode ;ignore decimal mode bit + cmp #(\1|faod)&m8 ;expected flags + always on bits + endm + eor_flag macro + ora #decmode ;ignore decimal mode bit + eor #\1|faod ;invert expected flags + always on bits + endm + endif + endif + + ;macros to set (register|memory|zeropage) & status + set_stat macro ;setting flags in the processor status register + load_flag \1 + pha ;use stack to load status + plp + endm + + set_a macro ;precharging accu & status + load_flag \2 + pha ;use stack to load status + lda #\1 ;precharge accu + plp + endm + + set_x macro ;precharging index & status + load_flag \2 + pha ;use stack to load status + ldx #\1 ;precharge index x + plp + endm + + set_y macro ;precharging index & status + load_flag \2 + pha ;use stack to load status + ldy #\1 ;precharge index y + plp + endm + + set_ax macro ;precharging indexed accu & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;precharge accu + plp + endm + + set_ay macro ;precharging indexed accu & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,y ;precharge accu + plp + endm + + set_z macro ;precharging indexed zp & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to zeropage + sta zpt + plp + endm + + set_zx macro ;precharging zp,x & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to indexed zeropage + sta zpt,x + plp + endm + + set_abs macro ;precharging indexed memory & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to memory + sta abst + plp + endm + + set_absx macro ;precharging abs,x & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to indexed memory + sta abst,x + plp + endm + + ;macros to test (register|memory|zeropage) & status & (mask) + tst_stat macro ;testing flags in the processor status register + php ;save status + pla ;use stack to retrieve status + pha + cmp_flag \1 + trap_ne + plp ;restore status + endm + + tst_a macro ;testing result in accu & flags + php ;save flags + cmp #\1 ;test result + trap_ne + pla ;load status + pha + cmp_flag \2 + trap_ne + plp ;restore status + endm + + tst_x macro ;testing result in x index & flags + php ;save flags + cpx #\1 ;test result + trap_ne + pla ;load status + pha + cmp_flag \2 + trap_ne + plp ;restore status + endm + + tst_y macro ;testing result in y index & flags + php ;save flags + cpy #\1 ;test result + trap_ne + pla ;load status + pha + cmp_flag \2 + trap_ne + plp ;restore status + endm + + tst_ax macro ;indexed testing result in accu & flags + php ;save flags + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne ; + endm + + tst_ay macro ;indexed testing result in accu & flags + php ;save flags + cmp \1,y ;test result + trap_ne ; + pla ;load status + eor_flag \3 + cmp \2,y ;test flags + trap_ne + endm + + tst_z macro ;indexed testing result in zp & flags + php ;save flags + lda zpt + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + + tst_zx macro ;testing result in zp,x & flags + php ;save flags + lda zpt,x + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + + tst_abs macro ;indexed testing result in memory & flags + php ;save flags + lda abst + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + + tst_absx macro ;testing result in abs,x & flags + php ;save flags + lda abst,x + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + + ; RAM integrity test + ; verifies that none of the previous tests has altered RAM outside of the + ; designated write areas. + ; uses zpt word as indirect pointer, zpt+2 word as checksum + if ram_top > -1 + check_ram macro + cld + lda #0 + sta zpt ;set low byte of indirect pointer + sta zpt+3 ;checksum high byte + if disable_selfmod = 0 + sta range_adr ;reset self modifying code + endif + clc + ldx #zp_bss-zero_page ;zeropage - write test area + ccs3\? adc zero_page,x + bcc ccs2\? + inc zpt+3 ;carry to high byte + clc + ccs2\? inx + bne ccs3\? + ldx #hi(abs1) ;set high byte of indirect pointer + stx zpt+1 + ldy #lo(abs1) ;data after write & execute test area + ccs5\? adc (zpt),y + bcc ccs4\? + inc zpt+3 ;carry to high byte + clc + ccs4\? iny + bne ccs5\? + inx ;advance RAM high address + stx zpt+1 + cpx #ram_top + bne ccs5\? + sta zpt+2 ;checksum low is + cmp ram_chksm ;checksum low expected + trap_ne ;checksum mismatch + lda zpt+3 ;checksum high is + cmp ram_chksm+1 ;checksum high expected + trap_ne ;checksum mismatch + endm + else + check_ram macro + ;RAM check disabled - RAM size not set + endm + endif + + next_test macro ;make sure, tests don't jump the fence + lda test_case ;previous test + cmp #test_num + trap_ne ;test is out of sequence + test_num = test_num + 1 + lda #test_num ;*** next tests' number + sta test_case + ;check_ram ;uncomment to find altered RAM after each test + endm + + if load_data_direct = 1 + data + else + bss ;uninitialized segment, copy of data at end of code! + endif + ; org zero_page +0000 = org 0 ;edited to provide binaries loading from 0 +0000 : 00000000000000.. ds zero_page + ;break test interrupt save +000a : 00 irq_a ds 1 ;a register +000b : 00 irq_x ds 1 ;x register + if I_flag = 2 + ;masking for I bit in status + flag_I_on ds 1 ;or mask to load flags + flag_I_off ds 1 ;and mask to load flags + endif +000c : zpt ;5 bytes store/modify test area + ;add/subtract operand generation and result/flag prediction +000c : 00 adfc ds 1 ;carry flag before op +000d : 00 ad1 ds 1 ;operand 1 - accumulator +000e : 00 ad2 ds 1 ;operand 2 - memory / immediate +000f : 00 adrl ds 1 ;expected result bits 0-7 +0010 : 00 adrh ds 1 ;expected result bit 8 (carry) +0011 : 00 adrf ds 1 ;expected flags NV0000ZC (only binary mode) +0012 : 00 sb2 ds 1 ;operand 2 complemented for subtract +0013 : zp_bss +0013 : c3824100 zp1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +0017 : 7f zp7f db $7f ;test pattern for compare + ;logical zeropage operands +0018 : 001f7180 zpOR db 0,$1f,$71,$80 ;test pattern for OR +001c : 0fff7f80 zpAN db $0f,$ff,$7f,$80 ;test pattern for AND +0020 : ff0f8f8f zpEO db $ff,$0f,$8f,$8f ;test pattern for EOR + ;indirect addressing pointers +0024 : 1702 ind1 dw abs1 ;indirect pointer to pattern in absolute memory +0026 : 1802 dw abs1+1 +0028 : 1902 dw abs1+2 +002a : 1a02 dw abs1+3 +002c : 1b02 dw abs7f +002e : 1f01 inw1 dw abs1-$f8 ;indirect pointer for wrap-test pattern +0030 : 0302 indt dw abst ;indirect pointer to store area in absolute memory +0032 : 0402 dw abst+1 +0034 : 0502 dw abst+2 +0036 : 0602 dw abst+3 +0038 : 0b01 inwt dw abst-$f8 ;indirect pointer for wrap-test store +003a : 4e02 indAN dw absAN ;indirect pointer to AND pattern in absolute memory +003c : 4f02 dw absAN+1 +003e : 5002 dw absAN+2 +0040 : 5102 dw absAN+3 +0042 : 5202 indEO dw absEO ;indirect pointer to EOR pattern in absolute memory +0044 : 5302 dw absEO+1 +0046 : 5402 dw absEO+2 +0048 : 5502 dw absEO+3 +004a : 4a02 indOR dw absOR ;indirect pointer to OR pattern in absolute memory +004c : 4b02 dw absOR+1 +004e : 4c02 dw absOR+2 +0050 : 4d02 dw absOR+3 + ;add/subtract indirect pointers +0052 : 0302 adi2 dw ada2 ;indirect pointer to operand 2 in absolute memory +0054 : 0402 sbi2 dw sba2 ;indirect pointer to complemented operand 2 (SBC) +0056 : 0401 adiy2 dw ada2-$ff ;with offset for indirect indexed +0058 : 0501 sbiy2 dw sba2-$ff +005a : zp_bss_end + +0200 = org data_segment +0200 : 00 test_case ds 1 ;current test number +0201 : 0000 ram_chksm ds 2 ;checksum for RAM integrity test + ;add/subtract operand copy - abs tests write area +0203 : abst ;5 bytes store/modify test area +0203 : 00 ada2 ds 1 ;operand 2 +0204 : 00 sba2 ds 1 ;operand 2 complemented for subtract +0205 : 000000 ds 3 ;fill remaining bytes +0208 : data_bss + if load_data_direct = 1 +0208 : 2900 ex_andi and #0 ;execute immediate opcodes +020a : 60 rts +020b : 4900 ex_eori eor #0 ;execute immediate opcodes +020d : 60 rts +020e : 0900 ex_orai ora #0 ;execute immediate opcodes +0210 : 60 rts +0211 : 6900 ex_adci adc #0 ;execute immediate opcodes +0213 : 60 rts +0214 : e900 ex_sbci sbc #0 ;execute immediate opcodes +0216 : 60 rts + else + ex_andi ds 3 + ex_eori ds 3 + ex_orai ds 3 + ex_adci ds 3 + ex_sbci ds 3 + endif +0217 : c3824100 abs1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +021b : 7f abs7f db $7f ;test pattern for compare + ;loads +021c : 80800002 fLDx db fn,fn,0,fz ;expected flags for load + ;shifts +0220 : rASL ;expected result ASL & ROL -carry +0220 : 86048200 rROL db $86,$04,$82,0 ; " +0224 : 87058301 rROLc db $87,$05,$83,1 ;expected result ROL +carry +0228 : rLSR ;expected result LSR & ROR -carry +0228 : 61412000 rROR db $61,$41,$20,0 ; " +022c : e1c1a080 rRORc db $e1,$c1,$a0,$80 ;expected result ROR +carry +0230 : fASL ;expected flags for shifts +0230 : 81018002 fROL db fnc,fc,fn,fz ;no carry in +0234 : 81018000 fROLc db fnc,fc,fn,0 ;carry in +0238 : fLSR +0238 : 01000102 fROR db fc,0,fc,fz ;no carry in +023c : 81808180 fRORc db fnc,fn,fnc,fn ;carry in + ;increments (decrements) +0240 : 7f80ff0001 rINC db $7f,$80,$ff,0,1 ;expected result for INC/DEC +0245 : 0080800200 fINC db 0,fn,fn,fz,0 ;expected flags for INC/DEC + ;logical memory operand +024a : 001f7180 absOR db 0,$1f,$71,$80 ;test pattern for OR +024e : 0fff7f80 absAN db $0f,$ff,$7f,$80 ;test pattern for AND +0252 : ff0f8f8f absEO db $ff,$0f,$8f,$8f ;test pattern for EOR + ;logical accu operand +0256 : 00f11f00 absORa db 0,$f1,$1f,0 ;test pattern for OR +025a : f0ffffff absANa db $f0,$ff,$ff,$ff ;test pattern for AND +025e : fff0f00f absEOa db $ff,$f0,$f0,$0f ;test pattern for EOR + ;logical results +0262 : 00ff7f80 absrlo db 0,$ff,$7f,$80 +0266 : 02800080 absflo db fz,fn,0,fn +026a : data_bss_end + + + code +0400 = org code_segment +0400 : d8 start cld +0401 : a2ff ldx #$ff +0403 : 9a txs +0404 : a900 lda #0 ;*** test 0 = initialize +0406 : 8d0002 sta test_case +0000 = test_num = 0 + + ;stop interrupts before initializing BSS + if I_flag = 1 + sei + endif + + ;initialize I/O for report channel + if report = 1 + jsr report_init + endif + + ;pretest small branch offset +0409 : a205 ldx #5 +040b : 4c3304 jmp psb_test +040e : psb_bwok +040e : a005 ldy #5 +0410 : d008 bne psb_forw + trap ;branch should be taken +0412 : 4c1204 > jmp * ;failed anyway + +0415 : 88 dey ;forward landing zone +0416 : 88 dey +0417 : 88 dey +0418 : 88 dey +0419 : 88 dey +041a : psb_forw +041a : 88 dey +041b : 88 dey +041c : 88 dey +041d : 88 dey +041e : 88 dey +041f : f017 beq psb_fwok + trap ;forward offset +0421 : 4c2104 > jmp * ;failed anyway + + +0424 : ca dex ;backward landing zone +0425 : ca dex +0426 : ca dex +0427 : ca dex +0428 : ca dex +0429 : psb_back +0429 : ca dex +042a : ca dex +042b : ca dex +042c : ca dex +042d : ca dex +042e : f0de beq psb_bwok + trap ;backward offset +0430 : 4c3004 > jmp * ;failed anyway + +0433 : psb_test +0433 : d0f4 bne psb_back + trap ;branch should be taken +0435 : 4c3504 > jmp * ;failed anyway + +0438 : psb_fwok + + ;initialize BSS segment + if load_data_direct != 1 + ldx #zp_end-zp_init-1 + ld_zp lda zp_init,x + sta zp_bss,x + dex + bpl ld_zp + ldx #data_end-data_init-1 + ld_data lda data_init,x + sta data_bss,x + dex + bpl ld_data + if ROM_vectors = 1 + ldx #5 + ld_vect lda vec_init,x + sta vec_bss,x + dex + bpl ld_vect + endif + endif + + ;retain status of interrupt flag + if I_flag = 2 + php + pla + and #4 ;isolate flag + sta flag_I_on ;or mask + eor #lo(~4) ;reverse + sta flag_I_off ;and mask + endif + + ;generate checksum for RAM integrity test + if ram_top > -1 + lda #0 + sta zpt ;set low byte of indirect pointer + sta ram_chksm+1 ;checksum high byte + if disable_selfmod = 0 + sta range_adr ;reset self modifying code + endif + clc + ldx #zp_bss-zero_page ;zeropage - write test area + gcs3 adc zero_page,x + bcc gcs2 + inc ram_chksm+1 ;carry to high byte + clc + gcs2 inx + bne gcs3 + ldx #hi(abs1) ;set high byte of indirect pointer + stx zpt+1 + ldy #lo(abs1) ;data after write & execute test area + gcs5 adc (zpt),y + bcc gcs4 + inc ram_chksm+1 ;carry to high byte + clc + gcs4 iny + bne gcs5 + inx ;advance RAM high address + stx zpt+1 + cpx #ram_top + bne gcs5 + sta ram_chksm ;checksum complete + endif + next_test +0438 : ad0002 > lda test_case ;previous test +043b : c900 > cmp #test_num + > trap_ne ;test is out of sequence +043d : d0fe > bne * ;failed not equal (non zero) + > +0001 = >test_num = test_num + 1 +043f : a901 > lda #test_num ;*** next tests' number +0441 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + if disable_selfmod = 0 + ;testing relative addressing with BEQ +0444 : a0fe ldy #$fe ;testing maximum range, not -1/-2 (invalid/self adr) +0446 : range_loop +0446 : 88 dey ;next relative address +0447 : 98 tya +0448 : aa tax ;precharge count to end of loop +0449 : 1008 bpl range_fw ;calculate relative address +044b : 18 clc ;avoid branch self or to relative address of branch +044c : 6902 adc #2 +044e : ea nop ;offset landing zone - tolerate +/-5 offset to branch +044f : ea nop +0450 : ea nop +0451 : ea nop +0452 : ea nop +0453 : range_fw +0453 : ea nop +0454 : ea nop +0455 : ea nop +0456 : ea nop +0457 : ea nop +0458 : 497f eor #$7f ;complement except sign +045a : 8de604 sta range_adr ;load into test target +045d : a900 lda #0 ;should set zero flag in status register +045f : 4ce504 jmp range_op + +0462 : ca dex ; offset landing zone - backward branch too far +0463 : ca dex +0464 : ca dex +0465 : ca dex +0466 : ca dex + ;relative address target field with branch under test in the middle +0467 : ca dex ;-128 - max backward +0468 : ca dex +0469 : ca dex +046a : ca dex +046b : ca dex +046c : ca dex +046d : ca dex +046e : ca dex +046f : ca dex ;-120 +0470 : ca dex +0471 : ca dex +0472 : ca dex +0473 : ca dex +0474 : ca dex +0475 : ca dex +0476 : ca dex +0477 : ca dex +0478 : ca dex +0479 : ca dex ;-110 +047a : ca dex +047b : ca dex +047c : ca dex +047d : ca dex +047e : ca dex +047f : ca dex +0480 : ca dex +0481 : ca dex +0482 : ca dex +0483 : ca dex ;-100 +0484 : ca dex +0485 : ca dex +0486 : ca dex +0487 : ca dex +0488 : ca dex +0489 : ca dex +048a : ca dex +048b : ca dex +048c : ca dex +048d : ca dex ;-90 +048e : ca dex +048f : ca dex +0490 : ca dex +0491 : ca dex +0492 : ca dex +0493 : ca dex +0494 : ca dex +0495 : ca dex +0496 : ca dex +0497 : ca dex ;-80 +0498 : ca dex +0499 : ca dex +049a : ca dex +049b : ca dex +049c : ca dex +049d : ca dex +049e : ca dex +049f : ca dex +04a0 : ca dex +04a1 : ca dex ;-70 +04a2 : ca dex +04a3 : ca dex +04a4 : ca dex +04a5 : ca dex +04a6 : ca dex +04a7 : ca dex +04a8 : ca dex +04a9 : ca dex +04aa : ca dex +04ab : ca dex ;-60 +04ac : ca dex +04ad : ca dex +04ae : ca dex +04af : ca dex +04b0 : ca dex +04b1 : ca dex +04b2 : ca dex +04b3 : ca dex +04b4 : ca dex +04b5 : ca dex ;-50 +04b6 : ca dex +04b7 : ca dex +04b8 : ca dex +04b9 : ca dex +04ba : ca dex +04bb : ca dex +04bc : ca dex +04bd : ca dex +04be : ca dex +04bf : ca dex ;-40 +04c0 : ca dex +04c1 : ca dex +04c2 : ca dex +04c3 : ca dex +04c4 : ca dex +04c5 : ca dex +04c6 : ca dex +04c7 : ca dex +04c8 : ca dex +04c9 : ca dex ;-30 +04ca : ca dex +04cb : ca dex +04cc : ca dex +04cd : ca dex +04ce : ca dex +04cf : ca dex +04d0 : ca dex +04d1 : ca dex +04d2 : ca dex +04d3 : ca dex ;-20 +04d4 : ca dex +04d5 : ca dex +04d6 : ca dex +04d7 : ca dex +04d8 : ca dex +04d9 : ca dex +04da : ca dex +04db : ca dex +04dc : ca dex +04dd : ca dex ;-10 +04de : ca dex +04df : ca dex +04e0 : ca dex +04e1 : ca dex +04e2 : ca dex +04e3 : ca dex +04e4 : ca dex ;-3 +04e5 : range_op ;test target with zero flag=0, z=1 if previous dex +04e6 = range_adr = *+1 ;modifiable relative address +04e5 : f03e beq *+64 ;+64 if called without modification +04e7 : ca dex ;+0 +04e8 : ca dex +04e9 : ca dex +04ea : ca dex +04eb : ca dex +04ec : ca dex +04ed : ca dex +04ee : ca dex +04ef : ca dex +04f0 : ca dex +04f1 : ca dex ;+10 +04f2 : ca dex +04f3 : ca dex +04f4 : ca dex +04f5 : ca dex +04f6 : ca dex +04f7 : ca dex +04f8 : ca dex +04f9 : ca dex +04fa : ca dex +04fb : ca dex ;+20 +04fc : ca dex +04fd : ca dex +04fe : ca dex +04ff : ca dex +0500 : ca dex +0501 : ca dex +0502 : ca dex +0503 : ca dex +0504 : ca dex +0505 : ca dex ;+30 +0506 : ca dex +0507 : ca dex +0508 : ca dex +0509 : ca dex +050a : ca dex +050b : ca dex +050c : ca dex +050d : ca dex +050e : ca dex +050f : ca dex ;+40 +0510 : ca dex +0511 : ca dex +0512 : ca dex +0513 : ca dex +0514 : ca dex +0515 : ca dex +0516 : ca dex +0517 : ca dex +0518 : ca dex +0519 : ca dex ;+50 +051a : ca dex +051b : ca dex +051c : ca dex +051d : ca dex +051e : ca dex +051f : ca dex +0520 : ca dex +0521 : ca dex +0522 : ca dex +0523 : ca dex ;+60 +0524 : ca dex +0525 : ca dex +0526 : ca dex +0527 : ca dex +0528 : ca dex +0529 : ca dex +052a : ca dex +052b : ca dex +052c : ca dex +052d : ca dex ;+70 +052e : ca dex +052f : ca dex +0530 : ca dex +0531 : ca dex +0532 : ca dex +0533 : ca dex +0534 : ca dex +0535 : ca dex +0536 : ca dex +0537 : ca dex ;+80 +0538 : ca dex +0539 : ca dex +053a : ca dex +053b : ca dex +053c : ca dex +053d : ca dex +053e : ca dex +053f : ca dex +0540 : ca dex +0541 : ca dex ;+90 +0542 : ca dex +0543 : ca dex +0544 : ca dex +0545 : ca dex +0546 : ca dex +0547 : ca dex +0548 : ca dex +0549 : ca dex +054a : ca dex +054b : ca dex ;+100 +054c : ca dex +054d : ca dex +054e : ca dex +054f : ca dex +0550 : ca dex +0551 : ca dex +0552 : ca dex +0553 : ca dex +0554 : ca dex +0555 : ca dex ;+110 +0556 : ca dex +0557 : ca dex +0558 : ca dex +0559 : ca dex +055a : ca dex +055b : ca dex +055c : ca dex +055d : ca dex +055e : ca dex +055f : ca dex ;+120 +0560 : ca dex +0561 : ca dex +0562 : ca dex +0563 : ca dex +0564 : ca dex +0565 : ca dex +0566 : ea nop ;offset landing zone - forward branch too far +0567 : ea nop +0568 : ea nop +0569 : ea nop +056a : ea nop +056b : f008 beq range_ok ;+127 - max forward + trap ; bad range +056d : 4c6d05 > jmp * ;failed anyway + +0570 : ea nop ;offset landing zone - tolerate +/-5 offset to branch +0571 : ea nop +0572 : ea nop +0573 : ea nop +0574 : ea nop +0575 : range_ok +0575 : ea nop +0576 : ea nop +0577 : ea nop +0578 : ea nop +0579 : ea nop +057a : c000 cpy #0 +057c : f003 beq range_end +057e : 4c4604 jmp range_loop +0581 : range_end ;range test successful + endif + next_test +0581 : ad0002 > lda test_case ;previous test +0584 : c901 > cmp #test_num + > trap_ne ;test is out of sequence +0586 : d0fe > bne * ;failed not equal (non zero) + > +0002 = >test_num = test_num + 1 +0588 : a902 > lda #test_num ;*** next tests' number +058a : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ;partial test BNE & CMP, CPX, CPY immediate +058d : c001 cpy #1 ;testing BNE true +058f : d003 bne test_bne + trap +0591 : 4c9105 > jmp * ;failed anyway + +0594 : test_bne +0594 : a900 lda #0 +0596 : c900 cmp #0 ;test compare immediate + trap_ne +0598 : d0fe > bne * ;failed not equal (non zero) + + trap_cc +059a : 90fe > bcc * ;failed carry clear + + trap_mi +059c : 30fe > bmi * ;failed minus (bit 7 set) + +059e : c901 cmp #1 + trap_eq +05a0 : f0fe > beq * ;failed equal (zero) + + trap_cs +05a2 : b0fe > bcs * ;failed carry set + + trap_pl +05a4 : 10fe > bpl * ;failed plus (bit 7 clear) + +05a6 : aa tax +05a7 : e000 cpx #0 ;test compare x immediate + trap_ne +05a9 : d0fe > bne * ;failed not equal (non zero) + + trap_cc +05ab : 90fe > bcc * ;failed carry clear + + trap_mi +05ad : 30fe > bmi * ;failed minus (bit 7 set) + +05af : e001 cpx #1 + trap_eq +05b1 : f0fe > beq * ;failed equal (zero) + + trap_cs +05b3 : b0fe > bcs * ;failed carry set + + trap_pl +05b5 : 10fe > bpl * ;failed plus (bit 7 clear) + +05b7 : a8 tay +05b8 : c000 cpy #0 ;test compare y immediate + trap_ne +05ba : d0fe > bne * ;failed not equal (non zero) + + trap_cc +05bc : 90fe > bcc * ;failed carry clear + + trap_mi +05be : 30fe > bmi * ;failed minus (bit 7 set) + +05c0 : c001 cpy #1 + trap_eq +05c2 : f0fe > beq * ;failed equal (zero) + + trap_cs +05c4 : b0fe > bcs * ;failed carry set + + trap_pl +05c6 : 10fe > bpl * ;failed plus (bit 7 clear) + + next_test +05c8 : ad0002 > lda test_case ;previous test +05cb : c902 > cmp #test_num + > trap_ne ;test is out of sequence +05cd : d0fe > bne * ;failed not equal (non zero) + > +0003 = >test_num = test_num + 1 +05cf : a903 > lda #test_num ;*** next tests' number +05d1 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + ;testing stack operations PHA PHP PLA PLP + +05d4 : a2ff ldx #$ff ;initialize stack +05d6 : 9a txs +05d7 : a955 lda #$55 +05d9 : 48 pha +05da : a9aa lda #$aa +05dc : 48 pha +05dd : cdfe01 cmp $1fe ;on stack ? + trap_ne +05e0 : d0fe > bne * ;failed not equal (non zero) + +05e2 : ba tsx +05e3 : 8a txa ;overwrite accu +05e4 : c9fd cmp #$fd ;sp decremented? + trap_ne +05e6 : d0fe > bne * ;failed not equal (non zero) + +05e8 : 68 pla +05e9 : c9aa cmp #$aa ;successful retreived from stack? + trap_ne +05eb : d0fe > bne * ;failed not equal (non zero) + +05ed : 68 pla +05ee : c955 cmp #$55 + trap_ne +05f0 : d0fe > bne * ;failed not equal (non zero) + +05f2 : cdff01 cmp $1ff ;remains on stack? + trap_ne +05f5 : d0fe > bne * ;failed not equal (non zero) + +05f7 : ba tsx +05f8 : e0ff cpx #$ff ;sp incremented? + trap_ne +05fa : d0fe > bne * ;failed not equal (non zero) + + next_test +05fc : ad0002 > lda test_case ;previous test +05ff : c903 > cmp #test_num + > trap_ne ;test is out of sequence +0601 : d0fe > bne * ;failed not equal (non zero) + > +0004 = >test_num = test_num + 1 +0603 : a904 > lda #test_num ;*** next tests' number +0605 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ;testing branch decisions BPL BMI BVC BVS BCC BCS BNE BEQ + set_stat $ff ;all on + > load_flag $ff +0608 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +060a : 48 > pha ;use stack to load status +060b : 28 > plp + +060c : 101a bpl nbr1 ;branches should not be taken +060e : 501b bvc nbr2 +0610 : 901c bcc nbr3 +0612 : d01d bne nbr4 +0614 : 3003 bmi br1 ;branches should be taken + trap +0616 : 4c1606 > jmp * ;failed anyway + +0619 : 7003 br1 bvs br2 + trap +061b : 4c1b06 > jmp * ;failed anyway + +061e : b003 br2 bcs br3 + trap +0620 : 4c2006 > jmp * ;failed anyway + +0623 : f00f br3 beq br4 + trap +0625 : 4c2506 > jmp * ;failed anyway + +0628 : nbr1 + trap ;previous bpl taken +0628 : 4c2806 > jmp * ;failed anyway + +062b : nbr2 + trap ;previous bvc taken +062b : 4c2b06 > jmp * ;failed anyway + +062e : nbr3 + trap ;previous bcc taken +062e : 4c2e06 > jmp * ;failed anyway + +0631 : nbr4 + trap ;previous bne taken +0631 : 4c3106 > jmp * ;failed anyway + +0634 : 08 br4 php +0635 : ba tsx +0636 : e0fe cpx #$fe ;sp after php? + trap_ne +0638 : d0fe > bne * ;failed not equal (non zero) + +063a : 68 pla + cmp_flag $ff ;returned all flags on? +063b : c9ff > cmp #($ff |fao)&m8 ;expected flags + always on bits + + trap_ne +063d : d0fe > bne * ;failed not equal (non zero) + +063f : ba tsx +0640 : e0ff cpx #$ff ;sp after php? + trap_ne +0642 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 ;all off + > load_flag 0 +0644 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +0646 : 48 > pha ;use stack to load status +0647 : 28 > plp + +0648 : 301a bmi nbr11 ;branches should not be taken +064a : 701b bvs nbr12 +064c : b01c bcs nbr13 +064e : f01d beq nbr14 +0650 : 1003 bpl br11 ;branches should be taken + trap +0652 : 4c5206 > jmp * ;failed anyway + +0655 : 5003 br11 bvc br12 + trap +0657 : 4c5706 > jmp * ;failed anyway + +065a : 9003 br12 bcc br13 + trap +065c : 4c5c06 > jmp * ;failed anyway + +065f : d00f br13 bne br14 + trap +0661 : 4c6106 > jmp * ;failed anyway + +0664 : nbr11 + trap ;previous bmi taken +0664 : 4c6406 > jmp * ;failed anyway + +0667 : nbr12 + trap ;previous bvs taken +0667 : 4c6706 > jmp * ;failed anyway + +066a : nbr13 + trap ;previous bcs taken +066a : 4c6a06 > jmp * ;failed anyway + +066d : nbr14 + trap ;previous beq taken +066d : 4c6d06 > jmp * ;failed anyway + +0670 : 08 br14 php +0671 : 68 pla + cmp_flag 0 ;flags off except break (pushed by sw) + reserved? +0672 : c930 > cmp #(0 |fao)&m8 ;expected flags + always on bits + + trap_ne +0674 : d0fe > bne * ;failed not equal (non zero) + + ;crosscheck flags + set_stat zero + > load_flag zero +0676 : a902 > lda #zero ;allow test to change I-flag (no mask) + > +0678 : 48 > pha ;use stack to load status +0679 : 28 > plp + +067a : d002 bne brzs1 +067c : f003 beq brzs2 +067e : brzs1 + trap ;branch zero/non zero +067e : 4c7e06 > jmp * ;failed anyway + +0681 : b002 brzs2 bcs brzs3 +0683 : 9003 bcc brzs4 +0685 : brzs3 + trap ;branch carry/no carry +0685 : 4c8506 > jmp * ;failed anyway + +0688 : 3002 brzs4 bmi brzs5 +068a : 1003 bpl brzs6 +068c : brzs5 + trap ;branch minus/plus +068c : 4c8c06 > jmp * ;failed anyway + +068f : 7002 brzs6 bvs brzs7 +0691 : 5003 bvc brzs8 +0693 : brzs7 + trap ;branch overflow/no overflow +0693 : 4c9306 > jmp * ;failed anyway + +0696 : brzs8 + set_stat carry + > load_flag carry +0696 : a901 > lda #carry ;allow test to change I-flag (no mask) + > +0698 : 48 > pha ;use stack to load status +0699 : 28 > plp + +069a : f002 beq brcs1 +069c : d003 bne brcs2 +069e : brcs1 + trap ;branch zero/non zero +069e : 4c9e06 > jmp * ;failed anyway + +06a1 : 9002 brcs2 bcc brcs3 +06a3 : b003 bcs brcs4 +06a5 : brcs3 + trap ;branch carry/no carry +06a5 : 4ca506 > jmp * ;failed anyway + +06a8 : 3002 brcs4 bmi brcs5 +06aa : 1003 bpl brcs6 +06ac : brcs5 + trap ;branch minus/plus +06ac : 4cac06 > jmp * ;failed anyway + +06af : 7002 brcs6 bvs brcs7 +06b1 : 5003 bvc brcs8 +06b3 : brcs7 + trap ;branch overflow/no overflow +06b3 : 4cb306 > jmp * ;failed anyway + + +06b6 : brcs8 + set_stat minus + > load_flag minus +06b6 : a980 > lda #minus ;allow test to change I-flag (no mask) + > +06b8 : 48 > pha ;use stack to load status +06b9 : 28 > plp + +06ba : f002 beq brmi1 +06bc : d003 bne brmi2 +06be : brmi1 + trap ;branch zero/non zero +06be : 4cbe06 > jmp * ;failed anyway + +06c1 : b002 brmi2 bcs brmi3 +06c3 : 9003 bcc brmi4 +06c5 : brmi3 + trap ;branch carry/no carry +06c5 : 4cc506 > jmp * ;failed anyway + +06c8 : 1002 brmi4 bpl brmi5 +06ca : 3003 bmi brmi6 +06cc : brmi5 + trap ;branch minus/plus +06cc : 4ccc06 > jmp * ;failed anyway + +06cf : 7002 brmi6 bvs brmi7 +06d1 : 5003 bvc brmi8 +06d3 : brmi7 + trap ;branch overflow/no overflow +06d3 : 4cd306 > jmp * ;failed anyway + +06d6 : brmi8 + set_stat overfl + > load_flag overfl +06d6 : a940 > lda #overfl ;allow test to change I-flag (no mask) + > +06d8 : 48 > pha ;use stack to load status +06d9 : 28 > plp + +06da : f002 beq brvs1 +06dc : d003 bne brvs2 +06de : brvs1 + trap ;branch zero/non zero +06de : 4cde06 > jmp * ;failed anyway + +06e1 : b002 brvs2 bcs brvs3 +06e3 : 9003 bcc brvs4 +06e5 : brvs3 + trap ;branch carry/no carry +06e5 : 4ce506 > jmp * ;failed anyway + +06e8 : 3002 brvs4 bmi brvs5 +06ea : 1003 bpl brvs6 +06ec : brvs5 + trap ;branch minus/plus +06ec : 4cec06 > jmp * ;failed anyway + +06ef : 5002 brvs6 bvc brvs7 +06f1 : 7003 bvs brvs8 +06f3 : brvs7 + trap ;branch overflow/no overflow +06f3 : 4cf306 > jmp * ;failed anyway + +06f6 : brvs8 + set_stat $ff-zero + > load_flag $ff-zero +06f6 : a9fd > lda #$ff-zero ;allow test to change I-flag (no mask) + > +06f8 : 48 > pha ;use stack to load status +06f9 : 28 > plp + +06fa : f002 beq brzc1 +06fc : d003 bne brzc2 +06fe : brzc1 + trap ;branch zero/non zero +06fe : 4cfe06 > jmp * ;failed anyway + +0701 : 9002 brzc2 bcc brzc3 +0703 : b003 bcs brzc4 +0705 : brzc3 + trap ;branch carry/no carry +0705 : 4c0507 > jmp * ;failed anyway + +0708 : 1002 brzc4 bpl brzc5 +070a : 3003 bmi brzc6 +070c : brzc5 + trap ;branch minus/plus +070c : 4c0c07 > jmp * ;failed anyway + +070f : 5002 brzc6 bvc brzc7 +0711 : 7003 bvs brzc8 +0713 : brzc7 + trap ;branch overflow/no overflow +0713 : 4c1307 > jmp * ;failed anyway + +0716 : brzc8 + set_stat $ff-carry + > load_flag $ff-carry +0716 : a9fe > lda #$ff-carry ;allow test to change I-flag (no mask) + > +0718 : 48 > pha ;use stack to load status +0719 : 28 > plp + +071a : d002 bne brcc1 +071c : f003 beq brcc2 +071e : brcc1 + trap ;branch zero/non zero +071e : 4c1e07 > jmp * ;failed anyway + +0721 : b002 brcc2 bcs brcc3 +0723 : 9003 bcc brcc4 +0725 : brcc3 + trap ;branch carry/no carry +0725 : 4c2507 > jmp * ;failed anyway + +0728 : 1002 brcc4 bpl brcc5 +072a : 3003 bmi brcc6 +072c : brcc5 + trap ;branch minus/plus +072c : 4c2c07 > jmp * ;failed anyway + +072f : 5002 brcc6 bvc brcc7 +0731 : 7003 bvs brcc8 +0733 : brcc7 + trap ;branch overflow/no overflow +0733 : 4c3307 > jmp * ;failed anyway + +0736 : brcc8 + set_stat $ff-minus + > load_flag $ff-minus +0736 : a97f > lda #$ff-minus ;allow test to change I-flag (no mask) + > +0738 : 48 > pha ;use stack to load status +0739 : 28 > plp + +073a : d002 bne brpl1 +073c : f003 beq brpl2 +073e : brpl1 + trap ;branch zero/non zero +073e : 4c3e07 > jmp * ;failed anyway + +0741 : 9002 brpl2 bcc brpl3 +0743 : b003 bcs brpl4 +0745 : brpl3 + trap ;branch carry/no carry +0745 : 4c4507 > jmp * ;failed anyway + +0748 : 3002 brpl4 bmi brpl5 +074a : 1003 bpl brpl6 +074c : brpl5 + trap ;branch minus/plus +074c : 4c4c07 > jmp * ;failed anyway + +074f : 5002 brpl6 bvc brpl7 +0751 : 7003 bvs brpl8 +0753 : brpl7 + trap ;branch overflow/no overflow +0753 : 4c5307 > jmp * ;failed anyway + +0756 : brpl8 + set_stat $ff-overfl + > load_flag $ff-overfl +0756 : a9bf > lda #$ff-overfl ;allow test to change I-flag (no mask) + > +0758 : 48 > pha ;use stack to load status +0759 : 28 > plp + +075a : d002 bne brvc1 +075c : f003 beq brvc2 +075e : brvc1 + trap ;branch zero/non zero +075e : 4c5e07 > jmp * ;failed anyway + +0761 : 9002 brvc2 bcc brvc3 +0763 : b003 bcs brvc4 +0765 : brvc3 + trap ;branch carry/no carry +0765 : 4c6507 > jmp * ;failed anyway + +0768 : 1002 brvc4 bpl brvc5 +076a : 3003 bmi brvc6 +076c : brvc5 + trap ;branch minus/plus +076c : 4c6c07 > jmp * ;failed anyway + +076f : 7002 brvc6 bvs brvc7 +0771 : 5003 bvc brvc8 +0773 : brvc7 + trap ;branch overflow/no overflow +0773 : 4c7307 > jmp * ;failed anyway + +0776 : brvc8 + next_test +0776 : ad0002 > lda test_case ;previous test +0779 : c904 > cmp #test_num + > trap_ne ;test is out of sequence +077b : d0fe > bne * ;failed not equal (non zero) + > +0005 = >test_num = test_num + 1 +077d : a905 > lda #test_num ;*** next tests' number +077f : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; test PHA does not alter flags or accumulator but PLA does +0782 : a255 ldx #$55 ;x & y protected +0784 : a0aa ldy #$aa + set_a 1,$ff ;push + > load_flag $ff +0786 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +0788 : 48 > pha ;use stack to load status +0789 : a901 > lda #1 ;precharge accu +078b : 28 > plp + +078c : 48 pha + tst_a 1,$ff +078d : 08 > php ;save flags +078e : c901 > cmp #1 ;test result + > trap_ne +0790 : d0fe > bne * ;failed not equal (non zero) + > +0792 : 68 > pla ;load status +0793 : 48 > pha + > cmp_flag $ff +0794 : c9ff > cmp #($ff|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0796 : d0fe > bne * ;failed not equal (non zero) + > +0798 : 28 > plp ;restore status + + set_a 0,0 + > load_flag 0 +0799 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +079b : 48 > pha ;use stack to load status +079c : a900 > lda #0 ;precharge accu +079e : 28 > plp + +079f : 48 pha + tst_a 0,0 +07a0 : 08 > php ;save flags +07a1 : c900 > cmp #0 ;test result + > trap_ne +07a3 : d0fe > bne * ;failed not equal (non zero) + > +07a5 : 68 > pla ;load status +07a6 : 48 > pha + > cmp_flag 0 +07a7 : c930 > cmp #(0|fao)&m8 ;expected flags + always on bits + > + > trap_ne +07a9 : d0fe > bne * ;failed not equal (non zero) + > +07ab : 28 > plp ;restore status + + set_a $ff,$ff + > load_flag $ff +07ac : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +07ae : 48 > pha ;use stack to load status +07af : a9ff > lda #$ff ;precharge accu +07b1 : 28 > plp + +07b2 : 48 pha + tst_a $ff,$ff +07b3 : 08 > php ;save flags +07b4 : c9ff > cmp #$ff ;test result + > trap_ne +07b6 : d0fe > bne * ;failed not equal (non zero) + > +07b8 : 68 > pla ;load status +07b9 : 48 > pha + > cmp_flag $ff +07ba : c9ff > cmp #($ff|fao)&m8 ;expected flags + always on bits + > + > trap_ne +07bc : d0fe > bne * ;failed not equal (non zero) + > +07be : 28 > plp ;restore status + + set_a 1,0 + > load_flag 0 +07bf : a900 > lda #0 ;allow test to change I-flag (no mask) + > +07c1 : 48 > pha ;use stack to load status +07c2 : a901 > lda #1 ;precharge accu +07c4 : 28 > plp + +07c5 : 48 pha + tst_a 1,0 +07c6 : 08 > php ;save flags +07c7 : c901 > cmp #1 ;test result + > trap_ne +07c9 : d0fe > bne * ;failed not equal (non zero) + > +07cb : 68 > pla ;load status +07cc : 48 > pha + > cmp_flag 0 +07cd : c930 > cmp #(0|fao)&m8 ;expected flags + always on bits + > + > trap_ne +07cf : d0fe > bne * ;failed not equal (non zero) + > +07d1 : 28 > plp ;restore status + + set_a 0,$ff + > load_flag $ff +07d2 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +07d4 : 48 > pha ;use stack to load status +07d5 : a900 > lda #0 ;precharge accu +07d7 : 28 > plp + +07d8 : 48 pha + tst_a 0,$ff +07d9 : 08 > php ;save flags +07da : c900 > cmp #0 ;test result + > trap_ne +07dc : d0fe > bne * ;failed not equal (non zero) + > +07de : 68 > pla ;load status +07df : 48 > pha + > cmp_flag $ff +07e0 : c9ff > cmp #($ff|fao)&m8 ;expected flags + always on bits + > + > trap_ne +07e2 : d0fe > bne * ;failed not equal (non zero) + > +07e4 : 28 > plp ;restore status + + set_a $ff,0 + > load_flag 0 +07e5 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +07e7 : 48 > pha ;use stack to load status +07e8 : a9ff > lda #$ff ;precharge accu +07ea : 28 > plp + +07eb : 48 pha + tst_a $ff,0 +07ec : 08 > php ;save flags +07ed : c9ff > cmp #$ff ;test result + > trap_ne +07ef : d0fe > bne * ;failed not equal (non zero) + > +07f1 : 68 > pla ;load status +07f2 : 48 > pha + > cmp_flag 0 +07f3 : c930 > cmp #(0|fao)&m8 ;expected flags + always on bits + > + > trap_ne +07f5 : d0fe > bne * ;failed not equal (non zero) + > +07f7 : 28 > plp ;restore status + + set_a 0,$ff ;pull + > load_flag $ff +07f8 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +07fa : 48 > pha ;use stack to load status +07fb : a900 > lda #0 ;precharge accu +07fd : 28 > plp + +07fe : 68 pla + tst_a $ff,$ff-zero +07ff : 08 > php ;save flags +0800 : c9ff > cmp #$ff ;test result + > trap_ne +0802 : d0fe > bne * ;failed not equal (non zero) + > +0804 : 68 > pla ;load status +0805 : 48 > pha + > cmp_flag $ff-zero +0806 : c9fd > cmp #($ff-zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0808 : d0fe > bne * ;failed not equal (non zero) + > +080a : 28 > plp ;restore status + + set_a $ff,0 + > load_flag 0 +080b : a900 > lda #0 ;allow test to change I-flag (no mask) + > +080d : 48 > pha ;use stack to load status +080e : a9ff > lda #$ff ;precharge accu +0810 : 28 > plp + +0811 : 68 pla + tst_a 0,zero +0812 : 08 > php ;save flags +0813 : c900 > cmp #0 ;test result + > trap_ne +0815 : d0fe > bne * ;failed not equal (non zero) + > +0817 : 68 > pla ;load status +0818 : 48 > pha + > cmp_flag zero +0819 : c932 > cmp #(zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +081b : d0fe > bne * ;failed not equal (non zero) + > +081d : 28 > plp ;restore status + + set_a $fe,$ff + > load_flag $ff +081e : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +0820 : 48 > pha ;use stack to load status +0821 : a9fe > lda #$fe ;precharge accu +0823 : 28 > plp + +0824 : 68 pla + tst_a 1,$ff-zero-minus +0825 : 08 > php ;save flags +0826 : c901 > cmp #1 ;test result + > trap_ne +0828 : d0fe > bne * ;failed not equal (non zero) + > +082a : 68 > pla ;load status +082b : 48 > pha + > cmp_flag $ff-zero-minus +082c : c97d > cmp #($ff-zero-minus|fao)&m8 ;expected flags + always on bits + > + > trap_ne +082e : d0fe > bne * ;failed not equal (non zero) + > +0830 : 28 > plp ;restore status + + set_a 0,0 + > load_flag 0 +0831 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +0833 : 48 > pha ;use stack to load status +0834 : a900 > lda #0 ;precharge accu +0836 : 28 > plp + +0837 : 68 pla + tst_a $ff,minus +0838 : 08 > php ;save flags +0839 : c9ff > cmp #$ff ;test result + > trap_ne +083b : d0fe > bne * ;failed not equal (non zero) + > +083d : 68 > pla ;load status +083e : 48 > pha + > cmp_flag minus +083f : c9b0 > cmp #(minus|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0841 : d0fe > bne * ;failed not equal (non zero) + > +0843 : 28 > plp ;restore status + + set_a $ff,$ff + > load_flag $ff +0844 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +0846 : 48 > pha ;use stack to load status +0847 : a9ff > lda #$ff ;precharge accu +0849 : 28 > plp + +084a : 68 pla + tst_a 0,$ff-minus +084b : 08 > php ;save flags +084c : c900 > cmp #0 ;test result + > trap_ne +084e : d0fe > bne * ;failed not equal (non zero) + > +0850 : 68 > pla ;load status +0851 : 48 > pha + > cmp_flag $ff-minus +0852 : c97f > cmp #($ff-minus|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0854 : d0fe > bne * ;failed not equal (non zero) + > +0856 : 28 > plp ;restore status + + set_a $fe,0 + > load_flag 0 +0857 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +0859 : 48 > pha ;use stack to load status +085a : a9fe > lda #$fe ;precharge accu +085c : 28 > plp + +085d : 68 pla + tst_a 1,0 +085e : 08 > php ;save flags +085f : c901 > cmp #1 ;test result + > trap_ne +0861 : d0fe > bne * ;failed not equal (non zero) + > +0863 : 68 > pla ;load status +0864 : 48 > pha + > cmp_flag 0 +0865 : c930 > cmp #(0|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0867 : d0fe > bne * ;failed not equal (non zero) + > +0869 : 28 > plp ;restore status + +086a : e055 cpx #$55 ;x & y unchanged? + trap_ne +086c : d0fe > bne * ;failed not equal (non zero) + +086e : c0aa cpy #$aa + trap_ne +0870 : d0fe > bne * ;failed not equal (non zero) + + next_test +0872 : ad0002 > lda test_case ;previous test +0875 : c905 > cmp #test_num + > trap_ne ;test is out of sequence +0877 : d0fe > bne * ;failed not equal (non zero) + > +0006 = >test_num = test_num + 1 +0879 : a906 > lda #test_num ;*** next tests' number +087b : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; partial pretest EOR # + set_a $3c,0 + > load_flag 0 +087e : a900 > lda #0 ;allow test to change I-flag (no mask) + > +0880 : 48 > pha ;use stack to load status +0881 : a93c > lda #$3c ;precharge accu +0883 : 28 > plp + +0884 : 49c3 eor #$c3 + tst_a $ff,fn +0886 : 08 > php ;save flags +0887 : c9ff > cmp #$ff ;test result + > trap_ne +0889 : d0fe > bne * ;failed not equal (non zero) + > +088b : 68 > pla ;load status +088c : 48 > pha + > cmp_flag fn +088d : c9b0 > cmp #(fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +088f : d0fe > bne * ;failed not equal (non zero) + > +0891 : 28 > plp ;restore status + + set_a $c3,0 + > load_flag 0 +0892 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +0894 : 48 > pha ;use stack to load status +0895 : a9c3 > lda #$c3 ;precharge accu +0897 : 28 > plp + +0898 : 49c3 eor #$c3 + tst_a 0,fz +089a : 08 > php ;save flags +089b : c900 > cmp #0 ;test result + > trap_ne +089d : d0fe > bne * ;failed not equal (non zero) + > +089f : 68 > pla ;load status +08a0 : 48 > pha + > cmp_flag fz +08a1 : c932 > cmp #(fz|fao)&m8 ;expected flags + always on bits + > + > trap_ne +08a3 : d0fe > bne * ;failed not equal (non zero) + > +08a5 : 28 > plp ;restore status + + next_test +08a6 : ad0002 > lda test_case ;previous test +08a9 : c906 > cmp #test_num + > trap_ne ;test is out of sequence +08ab : d0fe > bne * ;failed not equal (non zero) + > +0007 = >test_num = test_num + 1 +08ad : a907 > lda #test_num ;*** next tests' number +08af : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; PC modifying instructions except branches (NOP, JMP, JSR, RTS, BRK, RTI) + ; testing NOP +08b2 : a224 ldx #$24 +08b4 : a042 ldy #$42 + set_a $18,0 + > load_flag 0 +08b6 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +08b8 : 48 > pha ;use stack to load status +08b9 : a918 > lda #$18 ;precharge accu +08bb : 28 > plp + +08bc : ea nop + tst_a $18,0 +08bd : 08 > php ;save flags +08be : c918 > cmp #$18 ;test result + > trap_ne +08c0 : d0fe > bne * ;failed not equal (non zero) + > +08c2 : 68 > pla ;load status +08c3 : 48 > pha + > cmp_flag 0 +08c4 : c930 > cmp #(0|fao)&m8 ;expected flags + always on bits + > + > trap_ne +08c6 : d0fe > bne * ;failed not equal (non zero) + > +08c8 : 28 > plp ;restore status + +08c9 : e024 cpx #$24 + trap_ne +08cb : d0fe > bne * ;failed not equal (non zero) + +08cd : c042 cpy #$42 + trap_ne +08cf : d0fe > bne * ;failed not equal (non zero) + +08d1 : a2db ldx #$db +08d3 : a0bd ldy #$bd + set_a $e7,$ff + > load_flag $ff +08d5 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +08d7 : 48 > pha ;use stack to load status +08d8 : a9e7 > lda #$e7 ;precharge accu +08da : 28 > plp + +08db : ea nop + tst_a $e7,$ff +08dc : 08 > php ;save flags +08dd : c9e7 > cmp #$e7 ;test result + > trap_ne +08df : d0fe > bne * ;failed not equal (non zero) + > +08e1 : 68 > pla ;load status +08e2 : 48 > pha + > cmp_flag $ff +08e3 : c9ff > cmp #($ff|fao)&m8 ;expected flags + always on bits + > + > trap_ne +08e5 : d0fe > bne * ;failed not equal (non zero) + > +08e7 : 28 > plp ;restore status + +08e8 : e0db cpx #$db + trap_ne +08ea : d0fe > bne * ;failed not equal (non zero) + +08ec : c0bd cpy #$bd + trap_ne +08ee : d0fe > bne * ;failed not equal (non zero) + + next_test +08f0 : ad0002 > lda test_case ;previous test +08f3 : c907 > cmp #test_num + > trap_ne ;test is out of sequence +08f5 : d0fe > bne * ;failed not equal (non zero) + > +0008 = >test_num = test_num + 1 +08f7 : a908 > lda #test_num ;*** next tests' number +08f9 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; jump absolute + set_stat $0 + > load_flag $0 +08fc : a900 > lda #$0 ;allow test to change I-flag (no mask) + > +08fe : 48 > pha ;use stack to load status +08ff : 28 > plp + +0900 : a946 lda #'F' +0902 : a241 ldx #'A' +0904 : a052 ldy #'R' ;N=0, V=0, Z=0, C=0 +0906 : 4cef36 jmp test_far +0909 : ea nop +090a : ea nop + trap_ne ;runover protection +090b : d0fe > bne * ;failed not equal (non zero) + +090d : e8 inx +090e : e8 inx +090f : far_ret + trap_eq ;returned flags OK? +090f : f0fe > beq * ;failed equal (zero) + + trap_pl +0911 : 10fe > bpl * ;failed plus (bit 7 clear) + + trap_cc +0913 : 90fe > bcc * ;failed carry clear + + trap_vc +0915 : 50fe > bvc * ;failed overflow clear + +0917 : c9ec cmp #('F'^$aa) ;returned registers OK? + trap_ne +0919 : d0fe > bne * ;failed not equal (non zero) + +091b : e042 cpx #('A'+1) + trap_ne +091d : d0fe > bne * ;failed not equal (non zero) + +091f : c04f cpy #('R'-3) + trap_ne +0921 : d0fe > bne * ;failed not equal (non zero) + +0923 : ca dex +0924 : c8 iny +0925 : c8 iny +0926 : c8 iny +0927 : 49aa eor #$aa ;N=0, V=1, Z=0, C=1 +0929 : 4c3209 jmp test_near +092c : ea nop +092d : ea nop + trap_ne ;runover protection +092e : d0fe > bne * ;failed not equal (non zero) + +0930 : e8 inx +0931 : e8 inx +0932 : test_near + trap_eq ;passed flags OK? +0932 : f0fe > beq * ;failed equal (zero) + + trap_mi +0934 : 30fe > bmi * ;failed minus (bit 7 set) + + trap_cc +0936 : 90fe > bcc * ;failed carry clear + + trap_vc +0938 : 50fe > bvc * ;failed overflow clear + +093a : c946 cmp #'F' ;passed registers OK? + trap_ne +093c : d0fe > bne * ;failed not equal (non zero) + +093e : e041 cpx #'A' + trap_ne +0940 : d0fe > bne * ;failed not equal (non zero) + +0942 : c052 cpy #'R' + trap_ne +0944 : d0fe > bne * ;failed not equal (non zero) + + next_test +0946 : ad0002 > lda test_case ;previous test +0949 : c908 > cmp #test_num + > trap_ne ;test is out of sequence +094b : d0fe > bne * ;failed not equal (non zero) + > +0009 = >test_num = test_num + 1 +094d : a909 > lda #test_num ;*** next tests' number +094f : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; jump indirect + set_stat 0 + > load_flag 0 +0952 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +0954 : 48 > pha ;use stack to load status +0955 : 28 > plp + +0956 : a949 lda #'I' +0958 : a24e ldx #'N' +095a : a044 ldy #'D' ;N=0, V=0, Z=0, C=0 +095c : 6c1e37 jmp (ptr_tst_ind) +095f : ea nop + trap_ne ;runover protection +0960 : d0fe > bne * ;failed not equal (non zero) + +0962 : 88 dey +0963 : 88 dey +0964 : ind_ret +0964 : 08 php ;either SP or Y count will fail, if we do not hit +0965 : 88 dey +0966 : 88 dey +0967 : 88 dey +0968 : 28 plp + trap_eq ;returned flags OK? +0969 : f0fe > beq * ;failed equal (zero) + + trap_pl +096b : 10fe > bpl * ;failed plus (bit 7 clear) + + trap_cc +096d : 90fe > bcc * ;failed carry clear + + trap_vc +096f : 50fe > bvc * ;failed overflow clear + +0971 : c9e3 cmp #('I'^$aa) ;returned registers OK? + trap_ne +0973 : d0fe > bne * ;failed not equal (non zero) + +0975 : e04f cpx #('N'+1) + trap_ne +0977 : d0fe > bne * ;failed not equal (non zero) + +0979 : c03e cpy #('D'-6) + trap_ne +097b : d0fe > bne * ;failed not equal (non zero) + +097d : ba tsx ;SP check +097e : e0ff cpx #$ff + trap_ne +0980 : d0fe > bne * ;failed not equal (non zero) + + next_test +0982 : ad0002 > lda test_case ;previous test +0985 : c909 > cmp #test_num + > trap_ne ;test is out of sequence +0987 : d0fe > bne * ;failed not equal (non zero) + > +000a = >test_num = test_num + 1 +0989 : a90a > lda #test_num ;*** next tests' number +098b : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; jump subroutine & return from subroutine + set_stat 0 + > load_flag 0 +098e : a900 > lda #0 ;allow test to change I-flag (no mask) + > +0990 : 48 > pha ;use stack to load status +0991 : 28 > plp + +0992 : a94a lda #'J' +0994 : a253 ldx #'S' +0996 : a052 ldy #'R' ;N=0, V=0, Z=0, C=0 +0998 : 205d37 jsr test_jsr +099a = jsr_ret = *-1 ;last address of jsr = return address +099b : 08 php ;either SP or Y count will fail, if we do not hit +099c : 88 dey +099d : 88 dey +099e : 88 dey +099f : 28 plp + trap_eq ;returned flags OK? +09a0 : f0fe > beq * ;failed equal (zero) + + trap_pl +09a2 : 10fe > bpl * ;failed plus (bit 7 clear) + + trap_cc +09a4 : 90fe > bcc * ;failed carry clear + + trap_vc +09a6 : 50fe > bvc * ;failed overflow clear + +09a8 : c9e0 cmp #('J'^$aa) ;returned registers OK? + trap_ne +09aa : d0fe > bne * ;failed not equal (non zero) + +09ac : e054 cpx #('S'+1) + trap_ne +09ae : d0fe > bne * ;failed not equal (non zero) + +09b0 : c04c cpy #('R'-6) + trap_ne +09b2 : d0fe > bne * ;failed not equal (non zero) + +09b4 : ba tsx ;sp? +09b5 : e0ff cpx #$ff + trap_ne +09b7 : d0fe > bne * ;failed not equal (non zero) + + next_test +09b9 : ad0002 > lda test_case ;previous test +09bc : c90a > cmp #test_num + > trap_ne ;test is out of sequence +09be : d0fe > bne * ;failed not equal (non zero) + > +000b = >test_num = test_num + 1 +09c0 : a90b > lda #test_num ;*** next tests' number +09c2 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; break & return from interrupt + if ROM_vectors = 1 + load_flag 0 ;with interrupts enabled if allowed! +09c5 : a900 > lda #0 ;allow test to change I-flag (no mask) + +09c7 : 48 pha +09c8 : a942 lda #'B' +09ca : a252 ldx #'R' +09cc : a04b ldy #'K' +09ce : 28 plp ;N=0, V=0, Z=0, C=0 +09cf : 00 brk + else + lda #hi brk_ret0 ;emulated break + pha + lda #lo brk_ret0 + pha + load_flag fao ;set break & unused on stack + pha + load_flag intdis ;during interrupt + pha + lda #'B' + ldx #'R' + ldy #'K' + plp ;N=0, V=0, Z=0, C=0 + jmp irq_trap + endif +09d0 : 88 dey ;should not be executed +09d1 : brk_ret0 ;address of break return +09d1 : 08 php ;either SP or Y count will fail, if we do not hit +09d2 : 88 dey +09d3 : 88 dey +09d4 : 88 dey +09d5 : c9e8 cmp #'B'^$aa ;returned registers OK? + ;the IRQ vector was never executed if A & X stay unmodified + trap_ne +09d7 : d0fe > bne * ;failed not equal (non zero) + +09d9 : e053 cpx #'R'+1 + trap_ne +09db : d0fe > bne * ;failed not equal (non zero) + +09dd : c045 cpy #'K'-6 + trap_ne +09df : d0fe > bne * ;failed not equal (non zero) + +09e1 : 68 pla ;returned flags OK (unchanged)? + cmp_flag 0 +09e2 : c930 > cmp #(0|fao)&m8 ;expected flags + always on bits + + trap_ne +09e4 : d0fe > bne * ;failed not equal (non zero) + +09e6 : ba tsx ;sp? +09e7 : e0ff cpx #$ff + trap_ne +09e9 : d0fe > bne * ;failed not equal (non zero) + + if ROM_vectors = 1 + load_flag $ff ;with interrupts disabled if allowed! +09eb : a9ff > lda #$ff ;allow test to change I-flag (no mask) + +09ed : 48 pha +09ee : a9bd lda #$ff-'B' +09f0 : a2ad ldx #$ff-'R' +09f2 : a0b4 ldy #$ff-'K' +09f4 : 28 plp ;N=1, V=1, Z=1, C=1 +09f5 : 00 brk + else + lda #hi brk_ret1 ;emulated break + pha + lda #lo brk_ret1 + pha + load_flag $ff + pha ;set break & unused on stack + pha ;actual flags + lda #$ff-'B' + ldx #$ff-'R' + ldy #$ff-'K' + plp ;N=1, V=1, Z=1, C=1 + jmp irq_trap + endif +09f6 : 88 dey ;should not be executed +09f7 : brk_ret1 ;address of break return +09f7 : 08 php ;either SP or Y count will fail, if we do not hit +09f8 : 88 dey +09f9 : 88 dey +09fa : 88 dey +09fb : c917 cmp #($ff-'B')^$aa ;returned registers OK? + ;the IRQ vector was never executed if A & X stay unmodified + trap_ne +09fd : d0fe > bne * ;failed not equal (non zero) + +09ff : e0ae cpx #$ff-'R'+1 + trap_ne +0a01 : d0fe > bne * ;failed not equal (non zero) + +0a03 : c0ae cpy #$ff-'K'-6 + trap_ne +0a05 : d0fe > bne * ;failed not equal (non zero) + +0a07 : 68 pla ;returned flags OK (unchanged)? + cmp_flag $ff +0a08 : c9ff > cmp #($ff|fao)&m8 ;expected flags + always on bits + + trap_ne +0a0a : d0fe > bne * ;failed not equal (non zero) + +0a0c : ba tsx ;sp? +0a0d : e0ff cpx #$ff + trap_ne +0a0f : d0fe > bne * ;failed not equal (non zero) + + next_test +0a11 : ad0002 > lda test_case ;previous test +0a14 : c90b > cmp #test_num + > trap_ne ;test is out of sequence +0a16 : d0fe > bne * ;failed not equal (non zero) + > +000c = >test_num = test_num + 1 +0a18 : a90c > lda #test_num ;*** next tests' number +0a1a : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; test set and clear flags CLC CLI CLD CLV SEC SEI SED + set_stat $ff + > load_flag $ff +0a1d : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +0a1f : 48 > pha ;use stack to load status +0a20 : 28 > plp + +0a21 : 18 clc + tst_stat $ff-carry +0a22 : 08 > php ;save status +0a23 : 68 > pla ;use stack to retrieve status +0a24 : 48 > pha + > cmp_flag $ff-carry +0a25 : c9fe > cmp #($ff-carry|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0a27 : d0fe > bne * ;failed not equal (non zero) + > +0a29 : 28 > plp ;restore status + +0a2a : 38 sec + tst_stat $ff +0a2b : 08 > php ;save status +0a2c : 68 > pla ;use stack to retrieve status +0a2d : 48 > pha + > cmp_flag $ff +0a2e : c9ff > cmp #($ff|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0a30 : d0fe > bne * ;failed not equal (non zero) + > +0a32 : 28 > plp ;restore status + + if I_flag = 3 +0a33 : 58 cli + tst_stat $ff-intdis +0a34 : 08 > php ;save status +0a35 : 68 > pla ;use stack to retrieve status +0a36 : 48 > pha + > cmp_flag $ff-intdis +0a37 : c9fb > cmp #($ff-intdis|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0a39 : d0fe > bne * ;failed not equal (non zero) + > +0a3b : 28 > plp ;restore status + +0a3c : 78 sei + tst_stat $ff +0a3d : 08 > php ;save status +0a3e : 68 > pla ;use stack to retrieve status +0a3f : 48 > pha + > cmp_flag $ff +0a40 : c9ff > cmp #($ff|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0a42 : d0fe > bne * ;failed not equal (non zero) + > +0a44 : 28 > plp ;restore status + + endif +0a45 : d8 cld + tst_stat $ff-decmode +0a46 : 08 > php ;save status +0a47 : 68 > pla ;use stack to retrieve status +0a48 : 48 > pha + > cmp_flag $ff-decmode +0a49 : c9f7 > cmp #($ff-decmode|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0a4b : d0fe > bne * ;failed not equal (non zero) + > +0a4d : 28 > plp ;restore status + +0a4e : f8 sed + tst_stat $ff +0a4f : 08 > php ;save status +0a50 : 68 > pla ;use stack to retrieve status +0a51 : 48 > pha + > cmp_flag $ff +0a52 : c9ff > cmp #($ff|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0a54 : d0fe > bne * ;failed not equal (non zero) + > +0a56 : 28 > plp ;restore status + +0a57 : b8 clv + tst_stat $ff-overfl +0a58 : 08 > php ;save status +0a59 : 68 > pla ;use stack to retrieve status +0a5a : 48 > pha + > cmp_flag $ff-overfl +0a5b : c9bf > cmp #($ff-overfl|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0a5d : d0fe > bne * ;failed not equal (non zero) + > +0a5f : 28 > plp ;restore status + + set_stat 0 + > load_flag 0 +0a60 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +0a62 : 48 > pha ;use stack to load status +0a63 : 28 > plp + + tst_stat 0 +0a64 : 08 > php ;save status +0a65 : 68 > pla ;use stack to retrieve status +0a66 : 48 > pha + > cmp_flag 0 +0a67 : c930 > cmp #(0|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0a69 : d0fe > bne * ;failed not equal (non zero) + > +0a6b : 28 > plp ;restore status + +0a6c : 38 sec + tst_stat carry +0a6d : 08 > php ;save status +0a6e : 68 > pla ;use stack to retrieve status +0a6f : 48 > pha + > cmp_flag carry +0a70 : c931 > cmp #(carry|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0a72 : d0fe > bne * ;failed not equal (non zero) + > +0a74 : 28 > plp ;restore status + +0a75 : 18 clc + tst_stat 0 +0a76 : 08 > php ;save status +0a77 : 68 > pla ;use stack to retrieve status +0a78 : 48 > pha + > cmp_flag 0 +0a79 : c930 > cmp #(0 |fao)&m8 ;expected flags + always on bits + > + > trap_ne +0a7b : d0fe > bne * ;failed not equal (non zero) + > +0a7d : 28 > plp ;restore status + + if I_flag = 3 +0a7e : 78 sei + tst_stat intdis +0a7f : 08 > php ;save status +0a80 : 68 > pla ;use stack to retrieve status +0a81 : 48 > pha + > cmp_flag intdis +0a82 : c934 > cmp #(intdis|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0a84 : d0fe > bne * ;failed not equal (non zero) + > +0a86 : 28 > plp ;restore status + +0a87 : 58 cli + tst_stat 0 +0a88 : 08 > php ;save status +0a89 : 68 > pla ;use stack to retrieve status +0a8a : 48 > pha + > cmp_flag 0 +0a8b : c930 > cmp #(0|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0a8d : d0fe > bne * ;failed not equal (non zero) + > +0a8f : 28 > plp ;restore status + + endif +0a90 : f8 sed + tst_stat decmode +0a91 : 08 > php ;save status +0a92 : 68 > pla ;use stack to retrieve status +0a93 : 48 > pha + > cmp_flag decmode +0a94 : c938 > cmp #(decmode|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0a96 : d0fe > bne * ;failed not equal (non zero) + > +0a98 : 28 > plp ;restore status + +0a99 : d8 cld + tst_stat 0 +0a9a : 08 > php ;save status +0a9b : 68 > pla ;use stack to retrieve status +0a9c : 48 > pha + > cmp_flag 0 +0a9d : c930 > cmp #(0 |fao)&m8 ;expected flags + always on bits + > + > trap_ne +0a9f : d0fe > bne * ;failed not equal (non zero) + > +0aa1 : 28 > plp ;restore status + + set_stat overfl + > load_flag overfl +0aa2 : a940 > lda #overfl ;allow test to change I-flag (no mask) + > +0aa4 : 48 > pha ;use stack to load status +0aa5 : 28 > plp + + tst_stat overfl +0aa6 : 08 > php ;save status +0aa7 : 68 > pla ;use stack to retrieve status +0aa8 : 48 > pha + > cmp_flag overfl +0aa9 : c970 > cmp #(overfl|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0aab : d0fe > bne * ;failed not equal (non zero) + > +0aad : 28 > plp ;restore status + +0aae : b8 clv + tst_stat 0 +0aaf : 08 > php ;save status +0ab0 : 68 > pla ;use stack to retrieve status +0ab1 : 48 > pha + > cmp_flag 0 +0ab2 : c930 > cmp #(0|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0ab4 : d0fe > bne * ;failed not equal (non zero) + > +0ab6 : 28 > plp ;restore status + + next_test +0ab7 : ad0002 > lda test_case ;previous test +0aba : c90c > cmp #test_num + > trap_ne ;test is out of sequence +0abc : d0fe > bne * ;failed not equal (non zero) + > +000d = >test_num = test_num + 1 +0abe : a90d > lda #test_num ;*** next tests' number +0ac0 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + ; testing index register increment/decrement and transfer + ; INX INY DEX DEY TAX TXA TAY TYA +0ac3 : a2fe ldx #$fe + set_stat $ff + > load_flag $ff +0ac5 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +0ac7 : 48 > pha ;use stack to load status +0ac8 : 28 > plp + +0ac9 : e8 inx ;ff + tst_x $ff,$ff-zero +0aca : 08 > php ;save flags +0acb : e0ff > cpx #$ff ;test result + > trap_ne +0acd : d0fe > bne * ;failed not equal (non zero) + > +0acf : 68 > pla ;load status +0ad0 : 48 > pha + > cmp_flag $ff-zero +0ad1 : c9fd > cmp #($ff-zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0ad3 : d0fe > bne * ;failed not equal (non zero) + > +0ad5 : 28 > plp ;restore status + +0ad6 : e8 inx ;00 + tst_x 0,$ff-minus +0ad7 : 08 > php ;save flags +0ad8 : e000 > cpx #0 ;test result + > trap_ne +0ada : d0fe > bne * ;failed not equal (non zero) + > +0adc : 68 > pla ;load status +0add : 48 > pha + > cmp_flag $ff-minus +0ade : c97f > cmp #($ff-minus|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0ae0 : d0fe > bne * ;failed not equal (non zero) + > +0ae2 : 28 > plp ;restore status + +0ae3 : e8 inx ;01 + tst_x 1,$ff-minus-zero +0ae4 : 08 > php ;save flags +0ae5 : e001 > cpx #1 ;test result + > trap_ne +0ae7 : d0fe > bne * ;failed not equal (non zero) + > +0ae9 : 68 > pla ;load status +0aea : 48 > pha + > cmp_flag $ff-minus-zero +0aeb : c97d > cmp #($ff-minus-zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0aed : d0fe > bne * ;failed not equal (non zero) + > +0aef : 28 > plp ;restore status + +0af0 : ca dex ;00 + tst_x 0,$ff-minus +0af1 : 08 > php ;save flags +0af2 : e000 > cpx #0 ;test result + > trap_ne +0af4 : d0fe > bne * ;failed not equal (non zero) + > +0af6 : 68 > pla ;load status +0af7 : 48 > pha + > cmp_flag $ff-minus +0af8 : c97f > cmp #($ff-minus|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0afa : d0fe > bne * ;failed not equal (non zero) + > +0afc : 28 > plp ;restore status + +0afd : ca dex ;ff + tst_x $ff,$ff-zero +0afe : 08 > php ;save flags +0aff : e0ff > cpx #$ff ;test result + > trap_ne +0b01 : d0fe > bne * ;failed not equal (non zero) + > +0b03 : 68 > pla ;load status +0b04 : 48 > pha + > cmp_flag $ff-zero +0b05 : c9fd > cmp #($ff-zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0b07 : d0fe > bne * ;failed not equal (non zero) + > +0b09 : 28 > plp ;restore status + +0b0a : ca dex ;fe + set_stat 0 + > load_flag 0 +0b0b : a900 > lda #0 ;allow test to change I-flag (no mask) + > +0b0d : 48 > pha ;use stack to load status +0b0e : 28 > plp + +0b0f : e8 inx ;ff + tst_x $ff,minus +0b10 : 08 > php ;save flags +0b11 : e0ff > cpx #$ff ;test result + > trap_ne +0b13 : d0fe > bne * ;failed not equal (non zero) + > +0b15 : 68 > pla ;load status +0b16 : 48 > pha + > cmp_flag minus +0b17 : c9b0 > cmp #(minus|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0b19 : d0fe > bne * ;failed not equal (non zero) + > +0b1b : 28 > plp ;restore status + +0b1c : e8 inx ;00 + tst_x 0,zero +0b1d : 08 > php ;save flags +0b1e : e000 > cpx #0 ;test result + > trap_ne +0b20 : d0fe > bne * ;failed not equal (non zero) + > +0b22 : 68 > pla ;load status +0b23 : 48 > pha + > cmp_flag zero +0b24 : c932 > cmp #(zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0b26 : d0fe > bne * ;failed not equal (non zero) + > +0b28 : 28 > plp ;restore status + +0b29 : e8 inx ;01 + tst_x 1,0 +0b2a : 08 > php ;save flags +0b2b : e001 > cpx #1 ;test result + > trap_ne +0b2d : d0fe > bne * ;failed not equal (non zero) + > +0b2f : 68 > pla ;load status +0b30 : 48 > pha + > cmp_flag 0 +0b31 : c930 > cmp #(0|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0b33 : d0fe > bne * ;failed not equal (non zero) + > +0b35 : 28 > plp ;restore status + +0b36 : ca dex ;00 + tst_x 0,zero +0b37 : 08 > php ;save flags +0b38 : e000 > cpx #0 ;test result + > trap_ne +0b3a : d0fe > bne * ;failed not equal (non zero) + > +0b3c : 68 > pla ;load status +0b3d : 48 > pha + > cmp_flag zero +0b3e : c932 > cmp #(zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0b40 : d0fe > bne * ;failed not equal (non zero) + > +0b42 : 28 > plp ;restore status + +0b43 : ca dex ;ff + tst_x $ff,minus +0b44 : 08 > php ;save flags +0b45 : e0ff > cpx #$ff ;test result + > trap_ne +0b47 : d0fe > bne * ;failed not equal (non zero) + > +0b49 : 68 > pla ;load status +0b4a : 48 > pha + > cmp_flag minus +0b4b : c9b0 > cmp #(minus|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0b4d : d0fe > bne * ;failed not equal (non zero) + > +0b4f : 28 > plp ;restore status + + +0b50 : a0fe ldy #$fe + set_stat $ff + > load_flag $ff +0b52 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +0b54 : 48 > pha ;use stack to load status +0b55 : 28 > plp + +0b56 : c8 iny ;ff + tst_y $ff,$ff-zero +0b57 : 08 > php ;save flags +0b58 : c0ff > cpy #$ff ;test result + > trap_ne +0b5a : d0fe > bne * ;failed not equal (non zero) + > +0b5c : 68 > pla ;load status +0b5d : 48 > pha + > cmp_flag $ff-zero +0b5e : c9fd > cmp #($ff-zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0b60 : d0fe > bne * ;failed not equal (non zero) + > +0b62 : 28 > plp ;restore status + +0b63 : c8 iny ;00 + tst_y 0,$ff-minus +0b64 : 08 > php ;save flags +0b65 : c000 > cpy #0 ;test result + > trap_ne +0b67 : d0fe > bne * ;failed not equal (non zero) + > +0b69 : 68 > pla ;load status +0b6a : 48 > pha + > cmp_flag $ff-minus +0b6b : c97f > cmp #($ff-minus|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0b6d : d0fe > bne * ;failed not equal (non zero) + > +0b6f : 28 > plp ;restore status + +0b70 : c8 iny ;01 + tst_y 1,$ff-minus-zero +0b71 : 08 > php ;save flags +0b72 : c001 > cpy #1 ;test result + > trap_ne +0b74 : d0fe > bne * ;failed not equal (non zero) + > +0b76 : 68 > pla ;load status +0b77 : 48 > pha + > cmp_flag $ff-minus-zero +0b78 : c97d > cmp #($ff-minus-zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0b7a : d0fe > bne * ;failed not equal (non zero) + > +0b7c : 28 > plp ;restore status + +0b7d : 88 dey ;00 + tst_y 0,$ff-minus +0b7e : 08 > php ;save flags +0b7f : c000 > cpy #0 ;test result + > trap_ne +0b81 : d0fe > bne * ;failed not equal (non zero) + > +0b83 : 68 > pla ;load status +0b84 : 48 > pha + > cmp_flag $ff-minus +0b85 : c97f > cmp #($ff-minus|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0b87 : d0fe > bne * ;failed not equal (non zero) + > +0b89 : 28 > plp ;restore status + +0b8a : 88 dey ;ff + tst_y $ff,$ff-zero +0b8b : 08 > php ;save flags +0b8c : c0ff > cpy #$ff ;test result + > trap_ne +0b8e : d0fe > bne * ;failed not equal (non zero) + > +0b90 : 68 > pla ;load status +0b91 : 48 > pha + > cmp_flag $ff-zero +0b92 : c9fd > cmp #($ff-zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0b94 : d0fe > bne * ;failed not equal (non zero) + > +0b96 : 28 > plp ;restore status + +0b97 : 88 dey ;fe + set_stat 0 + > load_flag 0 +0b98 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +0b9a : 48 > pha ;use stack to load status +0b9b : 28 > plp + +0b9c : c8 iny ;ff + tst_y $ff,0+minus +0b9d : 08 > php ;save flags +0b9e : c0ff > cpy #$ff ;test result + > trap_ne +0ba0 : d0fe > bne * ;failed not equal (non zero) + > +0ba2 : 68 > pla ;load status +0ba3 : 48 > pha + > cmp_flag 0+minus +0ba4 : c9b0 > cmp #(0+minus|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0ba6 : d0fe > bne * ;failed not equal (non zero) + > +0ba8 : 28 > plp ;restore status + +0ba9 : c8 iny ;00 + tst_y 0,zero +0baa : 08 > php ;save flags +0bab : c000 > cpy #0 ;test result + > trap_ne +0bad : d0fe > bne * ;failed not equal (non zero) + > +0baf : 68 > pla ;load status +0bb0 : 48 > pha + > cmp_flag zero +0bb1 : c932 > cmp #(zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0bb3 : d0fe > bne * ;failed not equal (non zero) + > +0bb5 : 28 > plp ;restore status + +0bb6 : c8 iny ;01 + tst_y 1,0 +0bb7 : 08 > php ;save flags +0bb8 : c001 > cpy #1 ;test result + > trap_ne +0bba : d0fe > bne * ;failed not equal (non zero) + > +0bbc : 68 > pla ;load status +0bbd : 48 > pha + > cmp_flag 0 +0bbe : c930 > cmp #(0|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0bc0 : d0fe > bne * ;failed not equal (non zero) + > +0bc2 : 28 > plp ;restore status + +0bc3 : 88 dey ;00 + tst_y 0,zero +0bc4 : 08 > php ;save flags +0bc5 : c000 > cpy #0 ;test result + > trap_ne +0bc7 : d0fe > bne * ;failed not equal (non zero) + > +0bc9 : 68 > pla ;load status +0bca : 48 > pha + > cmp_flag zero +0bcb : c932 > cmp #(zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0bcd : d0fe > bne * ;failed not equal (non zero) + > +0bcf : 28 > plp ;restore status + +0bd0 : 88 dey ;ff + tst_y $ff,minus +0bd1 : 08 > php ;save flags +0bd2 : c0ff > cpy #$ff ;test result + > trap_ne +0bd4 : d0fe > bne * ;failed not equal (non zero) + > +0bd6 : 68 > pla ;load status +0bd7 : 48 > pha + > cmp_flag minus +0bd8 : c9b0 > cmp #(minus|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0bda : d0fe > bne * ;failed not equal (non zero) + > +0bdc : 28 > plp ;restore status + + +0bdd : a2ff ldx #$ff + set_stat $ff + > load_flag $ff +0bdf : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +0be1 : 48 > pha ;use stack to load status +0be2 : 28 > plp + +0be3 : 8a txa + tst_a $ff,$ff-zero +0be4 : 08 > php ;save flags +0be5 : c9ff > cmp #$ff ;test result + > trap_ne +0be7 : d0fe > bne * ;failed not equal (non zero) + > +0be9 : 68 > pla ;load status +0bea : 48 > pha + > cmp_flag $ff-zero +0beb : c9fd > cmp #($ff-zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0bed : d0fe > bne * ;failed not equal (non zero) + > +0bef : 28 > plp ;restore status + +0bf0 : 08 php +0bf1 : e8 inx ;00 +0bf2 : 28 plp +0bf3 : 8a txa + tst_a 0,$ff-minus +0bf4 : 08 > php ;save flags +0bf5 : c900 > cmp #0 ;test result + > trap_ne +0bf7 : d0fe > bne * ;failed not equal (non zero) + > +0bf9 : 68 > pla ;load status +0bfa : 48 > pha + > cmp_flag $ff-minus +0bfb : c97f > cmp #($ff-minus|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0bfd : d0fe > bne * ;failed not equal (non zero) + > +0bff : 28 > plp ;restore status + +0c00 : 08 php +0c01 : e8 inx ;01 +0c02 : 28 plp +0c03 : 8a txa + tst_a 1,$ff-minus-zero +0c04 : 08 > php ;save flags +0c05 : c901 > cmp #1 ;test result + > trap_ne +0c07 : d0fe > bne * ;failed not equal (non zero) + > +0c09 : 68 > pla ;load status +0c0a : 48 > pha + > cmp_flag $ff-minus-zero +0c0b : c97d > cmp #($ff-minus-zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0c0d : d0fe > bne * ;failed not equal (non zero) + > +0c0f : 28 > plp ;restore status + + set_stat 0 + > load_flag 0 +0c10 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +0c12 : 48 > pha ;use stack to load status +0c13 : 28 > plp + +0c14 : 8a txa + tst_a 1,0 +0c15 : 08 > php ;save flags +0c16 : c901 > cmp #1 ;test result + > trap_ne +0c18 : d0fe > bne * ;failed not equal (non zero) + > +0c1a : 68 > pla ;load status +0c1b : 48 > pha + > cmp_flag 0 +0c1c : c930 > cmp #(0|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0c1e : d0fe > bne * ;failed not equal (non zero) + > +0c20 : 28 > plp ;restore status + +0c21 : 08 php +0c22 : ca dex ;00 +0c23 : 28 plp +0c24 : 8a txa + tst_a 0,zero +0c25 : 08 > php ;save flags +0c26 : c900 > cmp #0 ;test result + > trap_ne +0c28 : d0fe > bne * ;failed not equal (non zero) + > +0c2a : 68 > pla ;load status +0c2b : 48 > pha + > cmp_flag zero +0c2c : c932 > cmp #(zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0c2e : d0fe > bne * ;failed not equal (non zero) + > +0c30 : 28 > plp ;restore status + +0c31 : 08 php +0c32 : ca dex ;ff +0c33 : 28 plp +0c34 : 8a txa + tst_a $ff,minus +0c35 : 08 > php ;save flags +0c36 : c9ff > cmp #$ff ;test result + > trap_ne +0c38 : d0fe > bne * ;failed not equal (non zero) + > +0c3a : 68 > pla ;load status +0c3b : 48 > pha + > cmp_flag minus +0c3c : c9b0 > cmp #(minus|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0c3e : d0fe > bne * ;failed not equal (non zero) + > +0c40 : 28 > plp ;restore status + + +0c41 : a0ff ldy #$ff + set_stat $ff + > load_flag $ff +0c43 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +0c45 : 48 > pha ;use stack to load status +0c46 : 28 > plp + +0c47 : 98 tya + tst_a $ff,$ff-zero +0c48 : 08 > php ;save flags +0c49 : c9ff > cmp #$ff ;test result + > trap_ne +0c4b : d0fe > bne * ;failed not equal (non zero) + > +0c4d : 68 > pla ;load status +0c4e : 48 > pha + > cmp_flag $ff-zero +0c4f : c9fd > cmp #($ff-zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0c51 : d0fe > bne * ;failed not equal (non zero) + > +0c53 : 28 > plp ;restore status + +0c54 : 08 php +0c55 : c8 iny ;00 +0c56 : 28 plp +0c57 : 98 tya + tst_a 0,$ff-minus +0c58 : 08 > php ;save flags +0c59 : c900 > cmp #0 ;test result + > trap_ne +0c5b : d0fe > bne * ;failed not equal (non zero) + > +0c5d : 68 > pla ;load status +0c5e : 48 > pha + > cmp_flag $ff-minus +0c5f : c97f > cmp #($ff-minus|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0c61 : d0fe > bne * ;failed not equal (non zero) + > +0c63 : 28 > plp ;restore status + +0c64 : 08 php +0c65 : c8 iny ;01 +0c66 : 28 plp +0c67 : 98 tya + tst_a 1,$ff-minus-zero +0c68 : 08 > php ;save flags +0c69 : c901 > cmp #1 ;test result + > trap_ne +0c6b : d0fe > bne * ;failed not equal (non zero) + > +0c6d : 68 > pla ;load status +0c6e : 48 > pha + > cmp_flag $ff-minus-zero +0c6f : c97d > cmp #($ff-minus-zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0c71 : d0fe > bne * ;failed not equal (non zero) + > +0c73 : 28 > plp ;restore status + + set_stat 0 + > load_flag 0 +0c74 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +0c76 : 48 > pha ;use stack to load status +0c77 : 28 > plp + +0c78 : 98 tya + tst_a 1,0 +0c79 : 08 > php ;save flags +0c7a : c901 > cmp #1 ;test result + > trap_ne +0c7c : d0fe > bne * ;failed not equal (non zero) + > +0c7e : 68 > pla ;load status +0c7f : 48 > pha + > cmp_flag 0 +0c80 : c930 > cmp #(0|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0c82 : d0fe > bne * ;failed not equal (non zero) + > +0c84 : 28 > plp ;restore status + +0c85 : 08 php +0c86 : 88 dey ;00 +0c87 : 28 plp +0c88 : 98 tya + tst_a 0,zero +0c89 : 08 > php ;save flags +0c8a : c900 > cmp #0 ;test result + > trap_ne +0c8c : d0fe > bne * ;failed not equal (non zero) + > +0c8e : 68 > pla ;load status +0c8f : 48 > pha + > cmp_flag zero +0c90 : c932 > cmp #(zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0c92 : d0fe > bne * ;failed not equal (non zero) + > +0c94 : 28 > plp ;restore status + +0c95 : 08 php +0c96 : 88 dey ;ff +0c97 : 28 plp +0c98 : 98 tya + tst_a $ff,minus +0c99 : 08 > php ;save flags +0c9a : c9ff > cmp #$ff ;test result + > trap_ne +0c9c : d0fe > bne * ;failed not equal (non zero) + > +0c9e : 68 > pla ;load status +0c9f : 48 > pha + > cmp_flag minus +0ca0 : c9b0 > cmp #(minus|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0ca2 : d0fe > bne * ;failed not equal (non zero) + > +0ca4 : 28 > plp ;restore status + + + load_flag $ff +0ca5 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + +0ca7 : 48 pha +0ca8 : a2ff ldx #$ff ;ff +0caa : 8a txa +0cab : 28 plp +0cac : a8 tay + tst_y $ff,$ff-zero +0cad : 08 > php ;save flags +0cae : c0ff > cpy #$ff ;test result + > trap_ne +0cb0 : d0fe > bne * ;failed not equal (non zero) + > +0cb2 : 68 > pla ;load status +0cb3 : 48 > pha + > cmp_flag $ff-zero +0cb4 : c9fd > cmp #($ff-zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0cb6 : d0fe > bne * ;failed not equal (non zero) + > +0cb8 : 28 > plp ;restore status + +0cb9 : 08 php +0cba : e8 inx ;00 +0cbb : 8a txa +0cbc : 28 plp +0cbd : a8 tay + tst_y 0,$ff-minus +0cbe : 08 > php ;save flags +0cbf : c000 > cpy #0 ;test result + > trap_ne +0cc1 : d0fe > bne * ;failed not equal (non zero) + > +0cc3 : 68 > pla ;load status +0cc4 : 48 > pha + > cmp_flag $ff-minus +0cc5 : c97f > cmp #($ff-minus|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0cc7 : d0fe > bne * ;failed not equal (non zero) + > +0cc9 : 28 > plp ;restore status + +0cca : 08 php +0ccb : e8 inx ;01 +0ccc : 8a txa +0ccd : 28 plp +0cce : a8 tay + tst_y 1,$ff-minus-zero +0ccf : 08 > php ;save flags +0cd0 : c001 > cpy #1 ;test result + > trap_ne +0cd2 : d0fe > bne * ;failed not equal (non zero) + > +0cd4 : 68 > pla ;load status +0cd5 : 48 > pha + > cmp_flag $ff-minus-zero +0cd6 : c97d > cmp #($ff-minus-zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0cd8 : d0fe > bne * ;failed not equal (non zero) + > +0cda : 28 > plp ;restore status + + load_flag 0 +0cdb : a900 > lda #0 ;allow test to change I-flag (no mask) + +0cdd : 48 pha +0cde : a900 lda #0 +0ce0 : 8a txa +0ce1 : 28 plp +0ce2 : a8 tay + tst_y 1,0 +0ce3 : 08 > php ;save flags +0ce4 : c001 > cpy #1 ;test result + > trap_ne +0ce6 : d0fe > bne * ;failed not equal (non zero) + > +0ce8 : 68 > pla ;load status +0ce9 : 48 > pha + > cmp_flag 0 +0cea : c930 > cmp #(0|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0cec : d0fe > bne * ;failed not equal (non zero) + > +0cee : 28 > plp ;restore status + +0cef : 08 php +0cf0 : ca dex ;00 +0cf1 : 8a txa +0cf2 : 28 plp +0cf3 : a8 tay + tst_y 0,zero +0cf4 : 08 > php ;save flags +0cf5 : c000 > cpy #0 ;test result + > trap_ne +0cf7 : d0fe > bne * ;failed not equal (non zero) + > +0cf9 : 68 > pla ;load status +0cfa : 48 > pha + > cmp_flag zero +0cfb : c932 > cmp #(zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0cfd : d0fe > bne * ;failed not equal (non zero) + > +0cff : 28 > plp ;restore status + +0d00 : 08 php +0d01 : ca dex ;ff +0d02 : 8a txa +0d03 : 28 plp +0d04 : a8 tay + tst_y $ff,minus +0d05 : 08 > php ;save flags +0d06 : c0ff > cpy #$ff ;test result + > trap_ne +0d08 : d0fe > bne * ;failed not equal (non zero) + > +0d0a : 68 > pla ;load status +0d0b : 48 > pha + > cmp_flag minus +0d0c : c9b0 > cmp #(minus|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0d0e : d0fe > bne * ;failed not equal (non zero) + > +0d10 : 28 > plp ;restore status + + + + load_flag $ff +0d11 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + +0d13 : 48 pha +0d14 : a0ff ldy #$ff ;ff +0d16 : 98 tya +0d17 : 28 plp +0d18 : aa tax + tst_x $ff,$ff-zero +0d19 : 08 > php ;save flags +0d1a : e0ff > cpx #$ff ;test result + > trap_ne +0d1c : d0fe > bne * ;failed not equal (non zero) + > +0d1e : 68 > pla ;load status +0d1f : 48 > pha + > cmp_flag $ff-zero +0d20 : c9fd > cmp #($ff-zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0d22 : d0fe > bne * ;failed not equal (non zero) + > +0d24 : 28 > plp ;restore status + +0d25 : 08 php +0d26 : c8 iny ;00 +0d27 : 98 tya +0d28 : 28 plp +0d29 : aa tax + tst_x 0,$ff-minus +0d2a : 08 > php ;save flags +0d2b : e000 > cpx #0 ;test result + > trap_ne +0d2d : d0fe > bne * ;failed not equal (non zero) + > +0d2f : 68 > pla ;load status +0d30 : 48 > pha + > cmp_flag $ff-minus +0d31 : c97f > cmp #($ff-minus|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0d33 : d0fe > bne * ;failed not equal (non zero) + > +0d35 : 28 > plp ;restore status + +0d36 : 08 php +0d37 : c8 iny ;01 +0d38 : 98 tya +0d39 : 28 plp +0d3a : aa tax + tst_x 1,$ff-minus-zero +0d3b : 08 > php ;save flags +0d3c : e001 > cpx #1 ;test result + > trap_ne +0d3e : d0fe > bne * ;failed not equal (non zero) + > +0d40 : 68 > pla ;load status +0d41 : 48 > pha + > cmp_flag $ff-minus-zero +0d42 : c97d > cmp #($ff-minus-zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0d44 : d0fe > bne * ;failed not equal (non zero) + > +0d46 : 28 > plp ;restore status + + load_flag 0 +0d47 : a900 > lda #0 ;allow test to change I-flag (no mask) + +0d49 : 48 pha +0d4a : a900 lda #0 ;preset status +0d4c : 98 tya +0d4d : 28 plp +0d4e : aa tax + tst_x 1,0 +0d4f : 08 > php ;save flags +0d50 : e001 > cpx #1 ;test result + > trap_ne +0d52 : d0fe > bne * ;failed not equal (non zero) + > +0d54 : 68 > pla ;load status +0d55 : 48 > pha + > cmp_flag 0 +0d56 : c930 > cmp #(0|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0d58 : d0fe > bne * ;failed not equal (non zero) + > +0d5a : 28 > plp ;restore status + +0d5b : 08 php +0d5c : 88 dey ;00 +0d5d : 98 tya +0d5e : 28 plp +0d5f : aa tax + tst_x 0,zero +0d60 : 08 > php ;save flags +0d61 : e000 > cpx #0 ;test result + > trap_ne +0d63 : d0fe > bne * ;failed not equal (non zero) + > +0d65 : 68 > pla ;load status +0d66 : 48 > pha + > cmp_flag zero +0d67 : c932 > cmp #(zero|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0d69 : d0fe > bne * ;failed not equal (non zero) + > +0d6b : 28 > plp ;restore status + +0d6c : 08 php +0d6d : 88 dey ;ff +0d6e : 98 tya +0d6f : 28 plp +0d70 : aa tax + tst_x $ff,minus +0d71 : 08 > php ;save flags +0d72 : e0ff > cpx #$ff ;test result + > trap_ne +0d74 : d0fe > bne * ;failed not equal (non zero) + > +0d76 : 68 > pla ;load status +0d77 : 48 > pha + > cmp_flag minus +0d78 : c9b0 > cmp #(minus|fao)&m8 ;expected flags + always on bits + > + > trap_ne +0d7a : d0fe > bne * ;failed not equal (non zero) + > +0d7c : 28 > plp ;restore status + + next_test +0d7d : ad0002 > lda test_case ;previous test +0d80 : c90d > cmp #test_num + > trap_ne ;test is out of sequence +0d82 : d0fe > bne * ;failed not equal (non zero) + > +000e = >test_num = test_num + 1 +0d84 : a90e > lda #test_num ;*** next tests' number +0d86 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ;TSX sets NZ - TXS does not + ; This section also tests for proper stack wrap around. +0d89 : a201 ldx #1 ;01 + set_stat $ff + > load_flag $ff +0d8b : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +0d8d : 48 > pha ;use stack to load status +0d8e : 28 > plp + +0d8f : 9a txs +0d90 : 08 php +0d91 : ad0101 lda $101 + cmp_flag $ff +0d94 : c9ff > cmp #($ff|fao)&m8 ;expected flags + always on bits + + trap_ne +0d96 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +0d98 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +0d9a : 48 > pha ;use stack to load status +0d9b : 28 > plp + +0d9c : 9a txs +0d9d : 08 php +0d9e : ad0101 lda $101 + cmp_flag 0 +0da1 : c930 > cmp #(0|fao)&m8 ;expected flags + always on bits + + trap_ne +0da3 : d0fe > bne * ;failed not equal (non zero) + +0da5 : ca dex ;00 + set_stat $ff + > load_flag $ff +0da6 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +0da8 : 48 > pha ;use stack to load status +0da9 : 28 > plp + +0daa : 9a txs +0dab : 08 php +0dac : ad0001 lda $100 + cmp_flag $ff +0daf : c9ff > cmp #($ff|fao)&m8 ;expected flags + always on bits + + trap_ne +0db1 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +0db3 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +0db5 : 48 > pha ;use stack to load status +0db6 : 28 > plp + +0db7 : 9a txs +0db8 : 08 php +0db9 : ad0001 lda $100 + cmp_flag 0 +0dbc : c930 > cmp #(0|fao)&m8 ;expected flags + always on bits + + trap_ne +0dbe : d0fe > bne * ;failed not equal (non zero) + +0dc0 : ca dex ;ff + set_stat $ff + > load_flag $ff +0dc1 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +0dc3 : 48 > pha ;use stack to load status +0dc4 : 28 > plp + +0dc5 : 9a txs +0dc6 : 08 php +0dc7 : adff01 lda $1ff + cmp_flag $ff +0dca : c9ff > cmp #($ff|fao)&m8 ;expected flags + always on bits + + trap_ne +0dcc : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +0dce : a900 > lda #0 ;allow test to change I-flag (no mask) + > +0dd0 : 48 > pha ;use stack to load status +0dd1 : 28 > plp + +0dd2 : 9a txs +0dd3 : 08 php +0dd4 : adff01 lda $1ff + cmp_flag 0 +0dd7 : c930 > cmp #(0|fao)&m8 ;expected flags + always on bits + + +0dd9 : a201 ldx #1 +0ddb : 9a txs ;sp=01 + set_stat $ff + > load_flag $ff +0ddc : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +0dde : 48 > pha ;use stack to load status +0ddf : 28 > plp + +0de0 : ba tsx ;clears Z, N +0de1 : 08 php ;sp=00 +0de2 : e001 cpx #1 + trap_ne +0de4 : d0fe > bne * ;failed not equal (non zero) + +0de6 : ad0101 lda $101 + cmp_flag $ff-minus-zero +0de9 : c97d > cmp #($ff-minus-zero|fao)&m8 ;expected flags + always on bits + + trap_ne +0deb : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +0ded : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +0def : 48 > pha ;use stack to load status +0df0 : 28 > plp + +0df1 : ba tsx ;clears N, sets Z +0df2 : 08 php ;sp=ff +0df3 : e000 cpx #0 + trap_ne +0df5 : d0fe > bne * ;failed not equal (non zero) + +0df7 : ad0001 lda $100 + cmp_flag $ff-minus +0dfa : c97f > cmp #($ff-minus|fao)&m8 ;expected flags + always on bits + + trap_ne +0dfc : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +0dfe : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +0e00 : 48 > pha ;use stack to load status +0e01 : 28 > plp + +0e02 : ba tsx ;clears N, sets Z +0e03 : 08 php ;sp=fe +0e04 : e0ff cpx #$ff + trap_ne +0e06 : d0fe > bne * ;failed not equal (non zero) + +0e08 : adff01 lda $1ff + cmp_flag $ff-zero +0e0b : c9fd > cmp #($ff-zero|fao)&m8 ;expected flags + always on bits + + trap_ne +0e0d : d0fe > bne * ;failed not equal (non zero) + + +0e0f : a201 ldx #1 +0e11 : 9a txs ;sp=01 + set_stat 0 + > load_flag 0 +0e12 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +0e14 : 48 > pha ;use stack to load status +0e15 : 28 > plp + +0e16 : ba tsx ;clears Z, N +0e17 : 08 php ;sp=00 +0e18 : e001 cpx #1 + trap_ne +0e1a : d0fe > bne * ;failed not equal (non zero) + +0e1c : ad0101 lda $101 + cmp_flag 0 +0e1f : c930 > cmp #(0|fao)&m8 ;expected flags + always on bits + + trap_ne +0e21 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +0e23 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +0e25 : 48 > pha ;use stack to load status +0e26 : 28 > plp + +0e27 : ba tsx ;clears N, sets Z +0e28 : 08 php ;sp=ff +0e29 : e000 cpx #0 + trap_ne +0e2b : d0fe > bne * ;failed not equal (non zero) + +0e2d : ad0001 lda $100 + cmp_flag zero +0e30 : c932 > cmp #(zero|fao)&m8 ;expected flags + always on bits + + trap_ne +0e32 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +0e34 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +0e36 : 48 > pha ;use stack to load status +0e37 : 28 > plp + +0e38 : ba tsx ;clears N, sets Z +0e39 : 08 php ;sp=fe +0e3a : e0ff cpx #$ff + trap_ne +0e3c : d0fe > bne * ;failed not equal (non zero) + +0e3e : adff01 lda $1ff + cmp_flag minus +0e41 : c9b0 > cmp #(minus|fao)&m8 ;expected flags + always on bits + + trap_ne +0e43 : d0fe > bne * ;failed not equal (non zero) + +0e45 : 68 pla ;sp=ff + next_test +0e46 : ad0002 > lda test_case ;previous test +0e49 : c90e > cmp #test_num + > trap_ne ;test is out of sequence +0e4b : d0fe > bne * ;failed not equal (non zero) + > +000f = >test_num = test_num + 1 +0e4d : a90f > lda #test_num ;*** next tests' number +0e4f : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; testing index register load & store LDY LDX STY STX all addressing modes + ; LDX / STX - zp,y / abs,y +0e52 : a003 ldy #3 +0e54 : tldx + set_stat 0 + > load_flag 0 +0e54 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +0e56 : 48 > pha ;use stack to load status +0e57 : 28 > plp + +0e58 : b613 ldx zp1,y +0e5a : 08 php ;test stores do not alter flags +0e5b : 8a txa +0e5c : 49c3 eor #$c3 +0e5e : 28 plp +0e5f : 990302 sta abst,y +0e62 : 08 php ;flags after load/store sequence +0e63 : 49c3 eor #$c3 +0e65 : d91702 cmp abs1,y ;test result + trap_ne +0e68 : d0fe > bne * ;failed not equal (non zero) + +0e6a : 68 pla ;load status + eor_flag 0 +0e6b : 4930 > eor #0|fao ;invert expected flags + always on bits + +0e6d : d91c02 cmp fLDx,y ;test flags + trap_ne +0e70 : d0fe > bne * ;failed not equal (non zero) + +0e72 : 88 dey +0e73 : 10df bpl tldx + +0e75 : a003 ldy #3 +0e77 : tldx1 + set_stat $ff + > load_flag $ff +0e77 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +0e79 : 48 > pha ;use stack to load status +0e7a : 28 > plp + +0e7b : b613 ldx zp1,y +0e7d : 08 php ;test stores do not alter flags +0e7e : 8a txa +0e7f : 49c3 eor #$c3 +0e81 : 28 plp +0e82 : 990302 sta abst,y +0e85 : 08 php ;flags after load/store sequence +0e86 : 49c3 eor #$c3 +0e88 : d91702 cmp abs1,y ;test result + trap_ne +0e8b : d0fe > bne * ;failed not equal (non zero) + +0e8d : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +0e8e : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +0e90 : d91c02 cmp fLDx,y ;test flags + trap_ne +0e93 : d0fe > bne * ;failed not equal (non zero) + +0e95 : 88 dey +0e96 : 10df bpl tldx1 + +0e98 : a003 ldy #3 +0e9a : tldx2 + set_stat 0 + > load_flag 0 +0e9a : a900 > lda #0 ;allow test to change I-flag (no mask) + > +0e9c : 48 > pha ;use stack to load status +0e9d : 28 > plp + +0e9e : be1702 ldx abs1,y +0ea1 : 08 php ;test stores do not alter flags +0ea2 : 8a txa +0ea3 : 49c3 eor #$c3 +0ea5 : aa tax +0ea6 : 28 plp +0ea7 : 960c stx zpt,y +0ea9 : 08 php ;flags after load/store sequence +0eaa : 49c3 eor #$c3 +0eac : d91300 cmp zp1,y ;test result + trap_ne +0eaf : d0fe > bne * ;failed not equal (non zero) + +0eb1 : 68 pla ;load status + eor_flag 0 +0eb2 : 4930 > eor #0|fao ;invert expected flags + always on bits + +0eb4 : d91c02 cmp fLDx,y ;test flags + trap_ne +0eb7 : d0fe > bne * ;failed not equal (non zero) + +0eb9 : 88 dey +0eba : 10de bpl tldx2 + +0ebc : a003 ldy #3 +0ebe : tldx3 + set_stat $ff + > load_flag $ff +0ebe : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +0ec0 : 48 > pha ;use stack to load status +0ec1 : 28 > plp + +0ec2 : be1702 ldx abs1,y +0ec5 : 08 php ;test stores do not alter flags +0ec6 : 8a txa +0ec7 : 49c3 eor #$c3 +0ec9 : aa tax +0eca : 28 plp +0ecb : 960c stx zpt,y +0ecd : 08 php ;flags after load/store sequence +0ece : 49c3 eor #$c3 +0ed0 : d91300 cmp zp1,y ;test result + trap_ne +0ed3 : d0fe > bne * ;failed not equal (non zero) + +0ed5 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +0ed6 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +0ed8 : d91c02 cmp fLDx,y ;test flags + trap_ne +0edb : d0fe > bne * ;failed not equal (non zero) + +0edd : 88 dey +0ede : 10de bpl tldx3 + +0ee0 : a003 ldy #3 ;testing store result +0ee2 : a200 ldx #0 +0ee4 : b90c00 tstx lda zpt,y +0ee7 : 49c3 eor #$c3 +0ee9 : d91300 cmp zp1,y + trap_ne ;store to zp data +0eec : d0fe > bne * ;failed not equal (non zero) + +0eee : 960c stx zpt,y ;clear +0ef0 : b90302 lda abst,y +0ef3 : 49c3 eor #$c3 +0ef5 : d91702 cmp abs1,y + trap_ne ;store to abs data +0ef8 : d0fe > bne * ;failed not equal (non zero) + +0efa : 8a txa +0efb : 990302 sta abst,y ;clear +0efe : 88 dey +0eff : 10e3 bpl tstx + next_test +0f01 : ad0002 > lda test_case ;previous test +0f04 : c90f > cmp #test_num + > trap_ne ;test is out of sequence +0f06 : d0fe > bne * ;failed not equal (non zero) + > +0010 = >test_num = test_num + 1 +0f08 : a910 > lda #test_num ;*** next tests' number +0f0a : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; indexed wraparound test (only zp should wrap) +0f0d : a0fd ldy #3+$fa +0f0f : b619 tldx4 ldx zp1-$fa&$ff,y ;wrap on indexed zp +0f11 : 8a txa +0f12 : 990901 sta abst-$fa,y ;no STX abs,y! +0f15 : 88 dey +0f16 : c0fa cpy #$fa +0f18 : b0f5 bcs tldx4 +0f1a : a0fd ldy #3+$fa +0f1c : be1d01 tldx5 ldx abs1-$fa,y ;no wrap on indexed abs +0f1f : 9612 stx zpt-$fa&$ff,y +0f21 : 88 dey +0f22 : c0fa cpy #$fa +0f24 : b0f6 bcs tldx5 +0f26 : a003 ldy #3 ;testing wraparound result +0f28 : a200 ldx #0 +0f2a : b90c00 tstx1 lda zpt,y +0f2d : d91300 cmp zp1,y + trap_ne ;store to zp data +0f30 : d0fe > bne * ;failed not equal (non zero) + +0f32 : 960c stx zpt,y ;clear +0f34 : b90302 lda abst,y +0f37 : d91702 cmp abs1,y + trap_ne ;store to abs data +0f3a : d0fe > bne * ;failed not equal (non zero) + +0f3c : 8a txa +0f3d : 990302 sta abst,y ;clear +0f40 : 88 dey +0f41 : 10e7 bpl tstx1 + next_test +0f43 : ad0002 > lda test_case ;previous test +0f46 : c910 > cmp #test_num + > trap_ne ;test is out of sequence +0f48 : d0fe > bne * ;failed not equal (non zero) + > +0011 = >test_num = test_num + 1 +0f4a : a911 > lda #test_num ;*** next tests' number +0f4c : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; LDY / STY - zp,x / abs,x +0f4f : a203 ldx #3 +0f51 : tldy + set_stat 0 + > load_flag 0 +0f51 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +0f53 : 48 > pha ;use stack to load status +0f54 : 28 > plp + +0f55 : b413 ldy zp1,x +0f57 : 08 php ;test stores do not alter flags +0f58 : 98 tya +0f59 : 49c3 eor #$c3 +0f5b : 28 plp +0f5c : 9d0302 sta abst,x +0f5f : 08 php ;flags after load/store sequence +0f60 : 49c3 eor #$c3 +0f62 : dd1702 cmp abs1,x ;test result + trap_ne +0f65 : d0fe > bne * ;failed not equal (non zero) + +0f67 : 68 pla ;load status + eor_flag 0 +0f68 : 4930 > eor #0|fao ;invert expected flags + always on bits + +0f6a : dd1c02 cmp fLDx,x ;test flags + trap_ne +0f6d : d0fe > bne * ;failed not equal (non zero) + +0f6f : ca dex +0f70 : 10df bpl tldy + +0f72 : a203 ldx #3 +0f74 : tldy1 + set_stat $ff + > load_flag $ff +0f74 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +0f76 : 48 > pha ;use stack to load status +0f77 : 28 > plp + +0f78 : b413 ldy zp1,x +0f7a : 08 php ;test stores do not alter flags +0f7b : 98 tya +0f7c : 49c3 eor #$c3 +0f7e : 28 plp +0f7f : 9d0302 sta abst,x +0f82 : 08 php ;flags after load/store sequence +0f83 : 49c3 eor #$c3 +0f85 : dd1702 cmp abs1,x ;test result + trap_ne +0f88 : d0fe > bne * ;failed not equal (non zero) + +0f8a : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +0f8b : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +0f8d : dd1c02 cmp fLDx,x ;test flags + trap_ne +0f90 : d0fe > bne * ;failed not equal (non zero) + +0f92 : ca dex +0f93 : 10df bpl tldy1 + +0f95 : a203 ldx #3 +0f97 : tldy2 + set_stat 0 + > load_flag 0 +0f97 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +0f99 : 48 > pha ;use stack to load status +0f9a : 28 > plp + +0f9b : bc1702 ldy abs1,x +0f9e : 08 php ;test stores do not alter flags +0f9f : 98 tya +0fa0 : 49c3 eor #$c3 +0fa2 : a8 tay +0fa3 : 28 plp +0fa4 : 940c sty zpt,x +0fa6 : 08 php ;flags after load/store sequence +0fa7 : 49c3 eor #$c3 +0fa9 : d513 cmp zp1,x ;test result + trap_ne +0fab : d0fe > bne * ;failed not equal (non zero) + +0fad : 68 pla ;load status + eor_flag 0 +0fae : 4930 > eor #0|fao ;invert expected flags + always on bits + +0fb0 : dd1c02 cmp fLDx,x ;test flags + trap_ne +0fb3 : d0fe > bne * ;failed not equal (non zero) + +0fb5 : ca dex +0fb6 : 10df bpl tldy2 + +0fb8 : a203 ldx #3 +0fba : tldy3 + set_stat $ff + > load_flag $ff +0fba : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +0fbc : 48 > pha ;use stack to load status +0fbd : 28 > plp + +0fbe : bc1702 ldy abs1,x +0fc1 : 08 php ;test stores do not alter flags +0fc2 : 98 tya +0fc3 : 49c3 eor #$c3 +0fc5 : a8 tay +0fc6 : 28 plp +0fc7 : 940c sty zpt,x +0fc9 : 08 php ;flags after load/store sequence +0fca : 49c3 eor #$c3 +0fcc : d513 cmp zp1,x ;test result + trap_ne +0fce : d0fe > bne * ;failed not equal (non zero) + +0fd0 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +0fd1 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +0fd3 : dd1c02 cmp fLDx,x ;test flags + trap_ne +0fd6 : d0fe > bne * ;failed not equal (non zero) + +0fd8 : ca dex +0fd9 : 10df bpl tldy3 + +0fdb : a203 ldx #3 ;testing store result +0fdd : a000 ldy #0 +0fdf : b50c tsty lda zpt,x +0fe1 : 49c3 eor #$c3 +0fe3 : d513 cmp zp1,x + trap_ne ;store to zp,x data +0fe5 : d0fe > bne * ;failed not equal (non zero) + +0fe7 : 940c sty zpt,x ;clear +0fe9 : bd0302 lda abst,x +0fec : 49c3 eor #$c3 +0fee : dd1702 cmp abs1,x + trap_ne ;store to abs,x data +0ff1 : d0fe > bne * ;failed not equal (non zero) + +0ff3 : 8a txa +0ff4 : 9d0302 sta abst,x ;clear +0ff7 : ca dex +0ff8 : 10e5 bpl tsty + next_test +0ffa : ad0002 > lda test_case ;previous test +0ffd : c911 > cmp #test_num + > trap_ne ;test is out of sequence +0fff : d0fe > bne * ;failed not equal (non zero) + > +0012 = >test_num = test_num + 1 +1001 : a912 > lda #test_num ;*** next tests' number +1003 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; indexed wraparound test (only zp should wrap) +1006 : a2fd ldx #3+$fa +1008 : b419 tldy4 ldy zp1-$fa&$ff,x ;wrap on indexed zp +100a : 98 tya +100b : 9d0901 sta abst-$fa,x ;no STX abs,x! +100e : ca dex +100f : e0fa cpx #$fa +1011 : b0f5 bcs tldy4 +1013 : a2fd ldx #3+$fa +1015 : bc1d01 tldy5 ldy abs1-$fa,x ;no wrap on indexed abs +1018 : 9412 sty zpt-$fa&$ff,x +101a : ca dex +101b : e0fa cpx #$fa +101d : b0f6 bcs tldy5 +101f : a203 ldx #3 ;testing wraparound result +1021 : a000 ldy #0 +1023 : b50c tsty1 lda zpt,x +1025 : d513 cmp zp1,x + trap_ne ;store to zp,x data +1027 : d0fe > bne * ;failed not equal (non zero) + +1029 : 940c sty zpt,x ;clear +102b : bd0302 lda abst,x +102e : dd1702 cmp abs1,x + trap_ne ;store to abs,x data +1031 : d0fe > bne * ;failed not equal (non zero) + +1033 : 8a txa +1034 : 9d0302 sta abst,x ;clear +1037 : ca dex +1038 : 10e9 bpl tsty1 + next_test +103a : ad0002 > lda test_case ;previous test +103d : c912 > cmp #test_num + > trap_ne ;test is out of sequence +103f : d0fe > bne * ;failed not equal (non zero) + > +0013 = >test_num = test_num + 1 +1041 : a913 > lda #test_num ;*** next tests' number +1043 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; LDX / STX - zp / abs / # + set_stat 0 + > load_flag 0 +1046 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1048 : 48 > pha ;use stack to load status +1049 : 28 > plp + +104a : a613 ldx zp1 +104c : 08 php ;test stores do not alter flags +104d : 8a txa +104e : 49c3 eor #$c3 +1050 : aa tax +1051 : 28 plp +1052 : 8e0302 stx abst +1055 : 08 php ;flags after load/store sequence +1056 : 49c3 eor #$c3 +1058 : aa tax +1059 : e0c3 cpx #$c3 ;test result + trap_ne +105b : d0fe > bne * ;failed not equal (non zero) + +105d : 68 pla ;load status + eor_flag 0 +105e : 4930 > eor #0|fao ;invert expected flags + always on bits + +1060 : cd1c02 cmp fLDx ;test flags + trap_ne +1063 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +1065 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1067 : 48 > pha ;use stack to load status +1068 : 28 > plp + +1069 : a614 ldx zp1+1 +106b : 08 php ;test stores do not alter flags +106c : 8a txa +106d : 49c3 eor #$c3 +106f : aa tax +1070 : 28 plp +1071 : 8e0402 stx abst+1 +1074 : 08 php ;flags after load/store sequence +1075 : 49c3 eor #$c3 +1077 : aa tax +1078 : e082 cpx #$82 ;test result + trap_ne +107a : d0fe > bne * ;failed not equal (non zero) + +107c : 68 pla ;load status + eor_flag 0 +107d : 4930 > eor #0|fao ;invert expected flags + always on bits + +107f : cd1d02 cmp fLDx+1 ;test flags + trap_ne +1082 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +1084 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1086 : 48 > pha ;use stack to load status +1087 : 28 > plp + +1088 : a615 ldx zp1+2 +108a : 08 php ;test stores do not alter flags +108b : 8a txa +108c : 49c3 eor #$c3 +108e : aa tax +108f : 28 plp +1090 : 8e0502 stx abst+2 +1093 : 08 php ;flags after load/store sequence +1094 : 49c3 eor #$c3 +1096 : aa tax +1097 : e041 cpx #$41 ;test result + trap_ne +1099 : d0fe > bne * ;failed not equal (non zero) + +109b : 68 pla ;load status + eor_flag 0 +109c : 4930 > eor #0|fao ;invert expected flags + always on bits + +109e : cd1e02 cmp fLDx+2 ;test flags + trap_ne +10a1 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +10a3 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +10a5 : 48 > pha ;use stack to load status +10a6 : 28 > plp + +10a7 : a616 ldx zp1+3 +10a9 : 08 php ;test stores do not alter flags +10aa : 8a txa +10ab : 49c3 eor #$c3 +10ad : aa tax +10ae : 28 plp +10af : 8e0602 stx abst+3 +10b2 : 08 php ;flags after load/store sequence +10b3 : 49c3 eor #$c3 +10b5 : aa tax +10b6 : e000 cpx #0 ;test result + trap_ne +10b8 : d0fe > bne * ;failed not equal (non zero) + +10ba : 68 pla ;load status + eor_flag 0 +10bb : 4930 > eor #0|fao ;invert expected flags + always on bits + +10bd : cd1f02 cmp fLDx+3 ;test flags + trap_ne +10c0 : d0fe > bne * ;failed not equal (non zero) + + + set_stat $ff + > load_flag $ff +10c2 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +10c4 : 48 > pha ;use stack to load status +10c5 : 28 > plp + +10c6 : a613 ldx zp1 +10c8 : 08 php ;test stores do not alter flags +10c9 : 8a txa +10ca : 49c3 eor #$c3 +10cc : aa tax +10cd : 28 plp +10ce : 8e0302 stx abst +10d1 : 08 php ;flags after load/store sequence +10d2 : 49c3 eor #$c3 +10d4 : aa tax +10d5 : e0c3 cpx #$c3 ;test result + trap_ne ; +10d7 : d0fe > bne * ;failed not equal (non zero) + +10d9 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +10da : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +10dc : cd1c02 cmp fLDx ;test flags + trap_ne +10df : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +10e1 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +10e3 : 48 > pha ;use stack to load status +10e4 : 28 > plp + +10e5 : a614 ldx zp1+1 +10e7 : 08 php ;test stores do not alter flags +10e8 : 8a txa +10e9 : 49c3 eor #$c3 +10eb : aa tax +10ec : 28 plp +10ed : 8e0402 stx abst+1 +10f0 : 08 php ;flags after load/store sequence +10f1 : 49c3 eor #$c3 +10f3 : aa tax +10f4 : e082 cpx #$82 ;test result + trap_ne +10f6 : d0fe > bne * ;failed not equal (non zero) + +10f8 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +10f9 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +10fb : cd1d02 cmp fLDx+1 ;test flags + trap_ne +10fe : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +1100 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1102 : 48 > pha ;use stack to load status +1103 : 28 > plp + +1104 : a615 ldx zp1+2 +1106 : 08 php ;test stores do not alter flags +1107 : 8a txa +1108 : 49c3 eor #$c3 +110a : aa tax +110b : 28 plp +110c : 8e0502 stx abst+2 +110f : 08 php ;flags after load/store sequence +1110 : 49c3 eor #$c3 +1112 : aa tax +1113 : e041 cpx #$41 ;test result + trap_ne ; +1115 : d0fe > bne * ;failed not equal (non zero) + +1117 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +1118 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +111a : cd1e02 cmp fLDx+2 ;test flags + trap_ne +111d : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +111f : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1121 : 48 > pha ;use stack to load status +1122 : 28 > plp + +1123 : a616 ldx zp1+3 +1125 : 08 php ;test stores do not alter flags +1126 : 8a txa +1127 : 49c3 eor #$c3 +1129 : aa tax +112a : 28 plp +112b : 8e0602 stx abst+3 +112e : 08 php ;flags after load/store sequence +112f : 49c3 eor #$c3 +1131 : aa tax +1132 : e000 cpx #0 ;test result + trap_ne +1134 : d0fe > bne * ;failed not equal (non zero) + +1136 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +1137 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +1139 : cd1f02 cmp fLDx+3 ;test flags + trap_ne +113c : d0fe > bne * ;failed not equal (non zero) + + + set_stat 0 + > load_flag 0 +113e : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1140 : 48 > pha ;use stack to load status +1141 : 28 > plp + +1142 : ae1702 ldx abs1 +1145 : 08 php ;test stores do not alter flags +1146 : 8a txa +1147 : 49c3 eor #$c3 +1149 : aa tax +114a : 28 plp +114b : 860c stx zpt +114d : 08 php ;flags after load/store sequence +114e : 49c3 eor #$c3 +1150 : c513 cmp zp1 ;test result + trap_ne +1152 : d0fe > bne * ;failed not equal (non zero) + +1154 : 68 pla ;load status + eor_flag 0 +1155 : 4930 > eor #0|fao ;invert expected flags + always on bits + +1157 : cd1c02 cmp fLDx ;test flags + trap_ne +115a : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +115c : a900 > lda #0 ;allow test to change I-flag (no mask) + > +115e : 48 > pha ;use stack to load status +115f : 28 > plp + +1160 : ae1802 ldx abs1+1 +1163 : 08 php ;test stores do not alter flags +1164 : 8a txa +1165 : 49c3 eor #$c3 +1167 : aa tax +1168 : 28 plp +1169 : 860d stx zpt+1 +116b : 08 php ;flags after load/store sequence +116c : 49c3 eor #$c3 +116e : c514 cmp zp1+1 ;test result + trap_ne +1170 : d0fe > bne * ;failed not equal (non zero) + +1172 : 68 pla ;load status + eor_flag 0 +1173 : 4930 > eor #0|fao ;invert expected flags + always on bits + +1175 : cd1d02 cmp fLDx+1 ;test flags + trap_ne +1178 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +117a : a900 > lda #0 ;allow test to change I-flag (no mask) + > +117c : 48 > pha ;use stack to load status +117d : 28 > plp + +117e : ae1902 ldx abs1+2 +1181 : 08 php ;test stores do not alter flags +1182 : 8a txa +1183 : 49c3 eor #$c3 +1185 : aa tax +1186 : 28 plp +1187 : 860e stx zpt+2 +1189 : 08 php ;flags after load/store sequence +118a : 49c3 eor #$c3 +118c : c515 cmp zp1+2 ;test result + trap_ne +118e : d0fe > bne * ;failed not equal (non zero) + +1190 : 68 pla ;load status + eor_flag 0 +1191 : 4930 > eor #0|fao ;invert expected flags + always on bits + +1193 : cd1e02 cmp fLDx+2 ;test flags + trap_ne +1196 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +1198 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +119a : 48 > pha ;use stack to load status +119b : 28 > plp + +119c : ae1a02 ldx abs1+3 +119f : 08 php ;test stores do not alter flags +11a0 : 8a txa +11a1 : 49c3 eor #$c3 +11a3 : aa tax +11a4 : 28 plp +11a5 : 860f stx zpt+3 +11a7 : 08 php ;flags after load/store sequence +11a8 : 49c3 eor #$c3 +11aa : c516 cmp zp1+3 ;test result + trap_ne +11ac : d0fe > bne * ;failed not equal (non zero) + +11ae : 68 pla ;load status + eor_flag 0 +11af : 4930 > eor #0|fao ;invert expected flags + always on bits + +11b1 : cd1f02 cmp fLDx+3 ;test flags + trap_ne +11b4 : d0fe > bne * ;failed not equal (non zero) + + + set_stat $ff + > load_flag $ff +11b6 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +11b8 : 48 > pha ;use stack to load status +11b9 : 28 > plp + +11ba : ae1702 ldx abs1 +11bd : 08 php ;test stores do not alter flags +11be : 8a txa +11bf : 49c3 eor #$c3 +11c1 : aa tax +11c2 : 28 plp +11c3 : 860c stx zpt +11c5 : 08 php ;flags after load/store sequence +11c6 : 49c3 eor #$c3 +11c8 : aa tax +11c9 : e413 cpx zp1 ;test result + trap_ne +11cb : d0fe > bne * ;failed not equal (non zero) + +11cd : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +11ce : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +11d0 : cd1c02 cmp fLDx ;test flags + trap_ne +11d3 : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +11d5 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +11d7 : 48 > pha ;use stack to load status +11d8 : 28 > plp + +11d9 : ae1802 ldx abs1+1 +11dc : 08 php ;test stores do not alter flags +11dd : 8a txa +11de : 49c3 eor #$c3 +11e0 : aa tax +11e1 : 28 plp +11e2 : 860d stx zpt+1 +11e4 : 08 php ;flags after load/store sequence +11e5 : 49c3 eor #$c3 +11e7 : aa tax +11e8 : e414 cpx zp1+1 ;test result + trap_ne +11ea : d0fe > bne * ;failed not equal (non zero) + +11ec : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +11ed : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +11ef : cd1d02 cmp fLDx+1 ;test flags + trap_ne +11f2 : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +11f4 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +11f6 : 48 > pha ;use stack to load status +11f7 : 28 > plp + +11f8 : ae1902 ldx abs1+2 +11fb : 08 php ;test stores do not alter flags +11fc : 8a txa +11fd : 49c3 eor #$c3 +11ff : aa tax +1200 : 28 plp +1201 : 860e stx zpt+2 +1203 : 08 php ;flags after load/store sequence +1204 : 49c3 eor #$c3 +1206 : aa tax +1207 : e415 cpx zp1+2 ;test result + trap_ne +1209 : d0fe > bne * ;failed not equal (non zero) + +120b : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +120c : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +120e : cd1e02 cmp fLDx+2 ;test flags + trap_ne +1211 : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +1213 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1215 : 48 > pha ;use stack to load status +1216 : 28 > plp + +1217 : ae1a02 ldx abs1+3 +121a : 08 php ;test stores do not alter flags +121b : 8a txa +121c : 49c3 eor #$c3 +121e : aa tax +121f : 28 plp +1220 : 860f stx zpt+3 +1222 : 08 php ;flags after load/store sequence +1223 : 49c3 eor #$c3 +1225 : aa tax +1226 : e416 cpx zp1+3 ;test result + trap_ne +1228 : d0fe > bne * ;failed not equal (non zero) + +122a : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +122b : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +122d : cd1f02 cmp fLDx+3 ;test flags + trap_ne +1230 : d0fe > bne * ;failed not equal (non zero) + + + set_stat 0 + > load_flag 0 +1232 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1234 : 48 > pha ;use stack to load status +1235 : 28 > plp + +1236 : a2c3 ldx #$c3 +1238 : 08 php +1239 : ec1702 cpx abs1 ;test result + trap_ne +123c : d0fe > bne * ;failed not equal (non zero) + +123e : 68 pla ;load status + eor_flag 0 +123f : 4930 > eor #0|fao ;invert expected flags + always on bits + +1241 : cd1c02 cmp fLDx ;test flags + trap_ne +1244 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +1246 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1248 : 48 > pha ;use stack to load status +1249 : 28 > plp + +124a : a282 ldx #$82 +124c : 08 php +124d : ec1802 cpx abs1+1 ;test result + trap_ne +1250 : d0fe > bne * ;failed not equal (non zero) + +1252 : 68 pla ;load status + eor_flag 0 +1253 : 4930 > eor #0|fao ;invert expected flags + always on bits + +1255 : cd1d02 cmp fLDx+1 ;test flags + trap_ne +1258 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +125a : a900 > lda #0 ;allow test to change I-flag (no mask) + > +125c : 48 > pha ;use stack to load status +125d : 28 > plp + +125e : a241 ldx #$41 +1260 : 08 php +1261 : ec1902 cpx abs1+2 ;test result + trap_ne +1264 : d0fe > bne * ;failed not equal (non zero) + +1266 : 68 pla ;load status + eor_flag 0 +1267 : 4930 > eor #0|fao ;invert expected flags + always on bits + +1269 : cd1e02 cmp fLDx+2 ;test flags + trap_ne +126c : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +126e : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1270 : 48 > pha ;use stack to load status +1271 : 28 > plp + +1272 : a200 ldx #0 +1274 : 08 php +1275 : ec1a02 cpx abs1+3 ;test result + trap_ne +1278 : d0fe > bne * ;failed not equal (non zero) + +127a : 68 pla ;load status + eor_flag 0 +127b : 4930 > eor #0|fao ;invert expected flags + always on bits + +127d : cd1f02 cmp fLDx+3 ;test flags + trap_ne +1280 : d0fe > bne * ;failed not equal (non zero) + + + set_stat $ff + > load_flag $ff +1282 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1284 : 48 > pha ;use stack to load status +1285 : 28 > plp + +1286 : a2c3 ldx #$c3 +1288 : 08 php +1289 : ec1702 cpx abs1 ;test result + trap_ne +128c : d0fe > bne * ;failed not equal (non zero) + +128e : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +128f : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +1291 : cd1c02 cmp fLDx ;test flags + trap_ne +1294 : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +1296 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1298 : 48 > pha ;use stack to load status +1299 : 28 > plp + +129a : a282 ldx #$82 +129c : 08 php +129d : ec1802 cpx abs1+1 ;test result + trap_ne +12a0 : d0fe > bne * ;failed not equal (non zero) + +12a2 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +12a3 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +12a5 : cd1d02 cmp fLDx+1 ;test flags + trap_ne +12a8 : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +12aa : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +12ac : 48 > pha ;use stack to load status +12ad : 28 > plp + +12ae : a241 ldx #$41 +12b0 : 08 php +12b1 : ec1902 cpx abs1+2 ;test result + trap_ne +12b4 : d0fe > bne * ;failed not equal (non zero) + +12b6 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +12b7 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +12b9 : cd1e02 cmp fLDx+2 ;test flags + trap_ne +12bc : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +12be : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +12c0 : 48 > pha ;use stack to load status +12c1 : 28 > plp + +12c2 : a200 ldx #0 +12c4 : 08 php +12c5 : ec1a02 cpx abs1+3 ;test result + trap_ne +12c8 : d0fe > bne * ;failed not equal (non zero) + +12ca : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +12cb : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +12cd : cd1f02 cmp fLDx+3 ;test flags + trap_ne +12d0 : d0fe > bne * ;failed not equal (non zero) + + +12d2 : a200 ldx #0 +12d4 : a50c lda zpt +12d6 : 49c3 eor #$c3 +12d8 : c513 cmp zp1 + trap_ne ;store to zp data +12da : d0fe > bne * ;failed not equal (non zero) + +12dc : 860c stx zpt ;clear +12de : ad0302 lda abst +12e1 : 49c3 eor #$c3 +12e3 : cd1702 cmp abs1 + trap_ne ;store to abs data +12e6 : d0fe > bne * ;failed not equal (non zero) + +12e8 : 8e0302 stx abst ;clear +12eb : a50d lda zpt+1 +12ed : 49c3 eor #$c3 +12ef : c514 cmp zp1+1 + trap_ne ;store to zp data +12f1 : d0fe > bne * ;failed not equal (non zero) + +12f3 : 860d stx zpt+1 ;clear +12f5 : ad0402 lda abst+1 +12f8 : 49c3 eor #$c3 +12fa : cd1802 cmp abs1+1 + trap_ne ;store to abs data +12fd : d0fe > bne * ;failed not equal (non zero) + +12ff : 8e0402 stx abst+1 ;clear +1302 : a50e lda zpt+2 +1304 : 49c3 eor #$c3 +1306 : c515 cmp zp1+2 + trap_ne ;store to zp data +1308 : d0fe > bne * ;failed not equal (non zero) + +130a : 860e stx zpt+2 ;clear +130c : ad0502 lda abst+2 +130f : 49c3 eor #$c3 +1311 : cd1902 cmp abs1+2 + trap_ne ;store to abs data +1314 : d0fe > bne * ;failed not equal (non zero) + +1316 : 8e0502 stx abst+2 ;clear +1319 : a50f lda zpt+3 +131b : 49c3 eor #$c3 +131d : c516 cmp zp1+3 + trap_ne ;store to zp data +131f : d0fe > bne * ;failed not equal (non zero) + +1321 : 860f stx zpt+3 ;clear +1323 : ad0602 lda abst+3 +1326 : 49c3 eor #$c3 +1328 : cd1a02 cmp abs1+3 + trap_ne ;store to abs data +132b : d0fe > bne * ;failed not equal (non zero) + +132d : 8e0602 stx abst+3 ;clear + next_test +1330 : ad0002 > lda test_case ;previous test +1333 : c913 > cmp #test_num + > trap_ne ;test is out of sequence +1335 : d0fe > bne * ;failed not equal (non zero) + > +0014 = >test_num = test_num + 1 +1337 : a914 > lda #test_num ;*** next tests' number +1339 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; LDY / STY - zp / abs / # + set_stat 0 + > load_flag 0 +133c : a900 > lda #0 ;allow test to change I-flag (no mask) + > +133e : 48 > pha ;use stack to load status +133f : 28 > plp + +1340 : a413 ldy zp1 +1342 : 08 php ;test stores do not alter flags +1343 : 98 tya +1344 : 49c3 eor #$c3 +1346 : a8 tay +1347 : 28 plp +1348 : 8c0302 sty abst +134b : 08 php ;flags after load/store sequence +134c : 49c3 eor #$c3 +134e : a8 tay +134f : c0c3 cpy #$c3 ;test result + trap_ne +1351 : d0fe > bne * ;failed not equal (non zero) + +1353 : 68 pla ;load status + eor_flag 0 +1354 : 4930 > eor #0|fao ;invert expected flags + always on bits + +1356 : cd1c02 cmp fLDx ;test flags + trap_ne +1359 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +135b : a900 > lda #0 ;allow test to change I-flag (no mask) + > +135d : 48 > pha ;use stack to load status +135e : 28 > plp + +135f : a414 ldy zp1+1 +1361 : 08 php ;test stores do not alter flags +1362 : 98 tya +1363 : 49c3 eor #$c3 +1365 : a8 tay +1366 : 28 plp +1367 : 8c0402 sty abst+1 +136a : 08 php ;flags after load/store sequence +136b : 49c3 eor #$c3 +136d : a8 tay +136e : c082 cpy #$82 ;test result + trap_ne +1370 : d0fe > bne * ;failed not equal (non zero) + +1372 : 68 pla ;load status + eor_flag 0 +1373 : 4930 > eor #0|fao ;invert expected flags + always on bits + +1375 : cd1d02 cmp fLDx+1 ;test flags + trap_ne +1378 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +137a : a900 > lda #0 ;allow test to change I-flag (no mask) + > +137c : 48 > pha ;use stack to load status +137d : 28 > plp + +137e : a415 ldy zp1+2 +1380 : 08 php ;test stores do not alter flags +1381 : 98 tya +1382 : 49c3 eor #$c3 +1384 : a8 tay +1385 : 28 plp +1386 : 8c0502 sty abst+2 +1389 : 08 php ;flags after load/store sequence +138a : 49c3 eor #$c3 +138c : a8 tay +138d : c041 cpy #$41 ;test result + trap_ne +138f : d0fe > bne * ;failed not equal (non zero) + +1391 : 68 pla ;load status + eor_flag 0 +1392 : 4930 > eor #0|fao ;invert expected flags + always on bits + +1394 : cd1e02 cmp fLDx+2 ;test flags + trap_ne +1397 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +1399 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +139b : 48 > pha ;use stack to load status +139c : 28 > plp + +139d : a416 ldy zp1+3 +139f : 08 php ;test stores do not alter flags +13a0 : 98 tya +13a1 : 49c3 eor #$c3 +13a3 : a8 tay +13a4 : 28 plp +13a5 : 8c0602 sty abst+3 +13a8 : 08 php ;flags after load/store sequence +13a9 : 49c3 eor #$c3 +13ab : a8 tay +13ac : c000 cpy #0 ;test result + trap_ne +13ae : d0fe > bne * ;failed not equal (non zero) + +13b0 : 68 pla ;load status + eor_flag 0 +13b1 : 4930 > eor #0|fao ;invert expected flags + always on bits + +13b3 : cd1f02 cmp fLDx+3 ;test flags + trap_ne +13b6 : d0fe > bne * ;failed not equal (non zero) + + + set_stat $ff + > load_flag $ff +13b8 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +13ba : 48 > pha ;use stack to load status +13bb : 28 > plp + +13bc : a413 ldy zp1 +13be : 08 php ;test stores do not alter flags +13bf : 98 tya +13c0 : 49c3 eor #$c3 +13c2 : a8 tay +13c3 : 28 plp +13c4 : 8c0302 sty abst +13c7 : 08 php ;flags after load/store sequence +13c8 : 49c3 eor #$c3 +13ca : a8 tay +13cb : c0c3 cpy #$c3 ;test result + trap_ne +13cd : d0fe > bne * ;failed not equal (non zero) + +13cf : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +13d0 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +13d2 : cd1c02 cmp fLDx ;test flags + trap_ne +13d5 : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +13d7 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +13d9 : 48 > pha ;use stack to load status +13da : 28 > plp + +13db : a414 ldy zp1+1 +13dd : 08 php ;test stores do not alter flags +13de : 98 tya +13df : 49c3 eor #$c3 +13e1 : a8 tay +13e2 : 28 plp +13e3 : 8c0402 sty abst+1 +13e6 : 08 php ;flags after load/store sequence +13e7 : 49c3 eor #$c3 +13e9 : a8 tay +13ea : c082 cpy #$82 ;test result + trap_ne +13ec : d0fe > bne * ;failed not equal (non zero) + +13ee : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +13ef : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +13f1 : cd1d02 cmp fLDx+1 ;test flags + trap_ne +13f4 : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +13f6 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +13f8 : 48 > pha ;use stack to load status +13f9 : 28 > plp + +13fa : a415 ldy zp1+2 +13fc : 08 php ;test stores do not alter flags +13fd : 98 tya +13fe : 49c3 eor #$c3 +1400 : a8 tay +1401 : 28 plp +1402 : 8c0502 sty abst+2 +1405 : 08 php ;flags after load/store sequence +1406 : 49c3 eor #$c3 +1408 : a8 tay +1409 : c041 cpy #$41 ;test result + trap_ne +140b : d0fe > bne * ;failed not equal (non zero) + +140d : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +140e : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +1410 : cd1e02 cmp fLDx+2 ;test flags + trap_ne +1413 : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +1415 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1417 : 48 > pha ;use stack to load status +1418 : 28 > plp + +1419 : a416 ldy zp1+3 +141b : 08 php ;test stores do not alter flags +141c : 98 tya +141d : 49c3 eor #$c3 +141f : a8 tay +1420 : 28 plp +1421 : 8c0602 sty abst+3 +1424 : 08 php ;flags after load/store sequence +1425 : 49c3 eor #$c3 +1427 : a8 tay +1428 : c000 cpy #0 ;test result + trap_ne +142a : d0fe > bne * ;failed not equal (non zero) + +142c : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +142d : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +142f : cd1f02 cmp fLDx+3 ;test flags + trap_ne +1432 : d0fe > bne * ;failed not equal (non zero) + + + set_stat 0 + > load_flag 0 +1434 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1436 : 48 > pha ;use stack to load status +1437 : 28 > plp + +1438 : ac1702 ldy abs1 +143b : 08 php ;test stores do not alter flags +143c : 98 tya +143d : 49c3 eor #$c3 +143f : a8 tay +1440 : 28 plp +1441 : 840c sty zpt +1443 : 08 php ;flags after load/store sequence +1444 : 49c3 eor #$c3 +1446 : a8 tay +1447 : c413 cpy zp1 ;test result + trap_ne +1449 : d0fe > bne * ;failed not equal (non zero) + +144b : 68 pla ;load status + eor_flag 0 +144c : 4930 > eor #0|fao ;invert expected flags + always on bits + +144e : cd1c02 cmp fLDx ;test flags + trap_ne +1451 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +1453 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1455 : 48 > pha ;use stack to load status +1456 : 28 > plp + +1457 : ac1802 ldy abs1+1 +145a : 08 php ;test stores do not alter flags +145b : 98 tya +145c : 49c3 eor #$c3 +145e : a8 tay +145f : 28 plp +1460 : 840d sty zpt+1 +1462 : 08 php ;flags after load/store sequence +1463 : 49c3 eor #$c3 +1465 : a8 tay +1466 : c414 cpy zp1+1 ;test result + trap_ne +1468 : d0fe > bne * ;failed not equal (non zero) + +146a : 68 pla ;load status + eor_flag 0 +146b : 4930 > eor #0|fao ;invert expected flags + always on bits + +146d : cd1d02 cmp fLDx+1 ;test flags + trap_ne +1470 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +1472 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1474 : 48 > pha ;use stack to load status +1475 : 28 > plp + +1476 : ac1902 ldy abs1+2 +1479 : 08 php ;test stores do not alter flags +147a : 98 tya +147b : 49c3 eor #$c3 +147d : a8 tay +147e : 28 plp +147f : 840e sty zpt+2 +1481 : 08 php ;flags after load/store sequence +1482 : 49c3 eor #$c3 +1484 : a8 tay +1485 : c415 cpy zp1+2 ;test result + trap_ne +1487 : d0fe > bne * ;failed not equal (non zero) + +1489 : 68 pla ;load status + eor_flag 0 +148a : 4930 > eor #0|fao ;invert expected flags + always on bits + +148c : cd1e02 cmp fLDx+2 ;test flags + trap_ne +148f : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +1491 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1493 : 48 > pha ;use stack to load status +1494 : 28 > plp + +1495 : ac1a02 ldy abs1+3 +1498 : 08 php ;test stores do not alter flags +1499 : 98 tya +149a : 49c3 eor #$c3 +149c : a8 tay +149d : 28 plp +149e : 840f sty zpt+3 +14a0 : 08 php ;flags after load/store sequence +14a1 : 49c3 eor #$c3 +14a3 : a8 tay +14a4 : c416 cpy zp1+3 ;test result + trap_ne +14a6 : d0fe > bne * ;failed not equal (non zero) + +14a8 : 68 pla ;load status + eor_flag 0 +14a9 : 4930 > eor #0|fao ;invert expected flags + always on bits + +14ab : cd1f02 cmp fLDx+3 ;test flags + trap_ne +14ae : d0fe > bne * ;failed not equal (non zero) + + + set_stat $ff + > load_flag $ff +14b0 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +14b2 : 48 > pha ;use stack to load status +14b3 : 28 > plp + +14b4 : ac1702 ldy abs1 +14b7 : 08 php ;test stores do not alter flags +14b8 : 98 tya +14b9 : 49c3 eor #$c3 +14bb : a8 tay +14bc : 28 plp +14bd : 840c sty zpt +14bf : 08 php ;flags after load/store sequence +14c0 : 49c3 eor #$c3 +14c2 : a8 tay +14c3 : c513 cmp zp1 ;test result + trap_ne +14c5 : d0fe > bne * ;failed not equal (non zero) + +14c7 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +14c8 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +14ca : cd1c02 cmp fLDx ;test flags + trap_ne +14cd : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +14cf : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +14d1 : 48 > pha ;use stack to load status +14d2 : 28 > plp + +14d3 : ac1802 ldy abs1+1 +14d6 : 08 php ;test stores do not alter flags +14d7 : 98 tya +14d8 : 49c3 eor #$c3 +14da : a8 tay +14db : 28 plp +14dc : 840d sty zpt+1 +14de : 08 php ;flags after load/store sequence +14df : 49c3 eor #$c3 +14e1 : a8 tay +14e2 : c514 cmp zp1+1 ;test result + trap_ne +14e4 : d0fe > bne * ;failed not equal (non zero) + +14e6 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +14e7 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +14e9 : cd1d02 cmp fLDx+1 ;test flags + trap_ne +14ec : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +14ee : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +14f0 : 48 > pha ;use stack to load status +14f1 : 28 > plp + +14f2 : ac1902 ldy abs1+2 +14f5 : 08 php ;test stores do not alter flags +14f6 : 98 tya +14f7 : 49c3 eor #$c3 +14f9 : a8 tay +14fa : 28 plp +14fb : 840e sty zpt+2 +14fd : 08 php ;flags after load/store sequence +14fe : 49c3 eor #$c3 +1500 : a8 tay +1501 : c515 cmp zp1+2 ;test result + trap_ne +1503 : d0fe > bne * ;failed not equal (non zero) + +1505 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +1506 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +1508 : cd1e02 cmp fLDx+2 ;test flags + trap_ne +150b : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +150d : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +150f : 48 > pha ;use stack to load status +1510 : 28 > plp + +1511 : ac1a02 ldy abs1+3 +1514 : 08 php ;test stores do not alter flags +1515 : 98 tya +1516 : 49c3 eor #$c3 +1518 : a8 tay +1519 : 28 plp +151a : 840f sty zpt+3 +151c : 08 php ;flags after load/store sequence +151d : 49c3 eor #$c3 +151f : a8 tay +1520 : c516 cmp zp1+3 ;test result + trap_ne +1522 : d0fe > bne * ;failed not equal (non zero) + +1524 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +1525 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +1527 : cd1f02 cmp fLDx+3 ;test flags + trap_ne +152a : d0fe > bne * ;failed not equal (non zero) + + + + set_stat 0 + > load_flag 0 +152c : a900 > lda #0 ;allow test to change I-flag (no mask) + > +152e : 48 > pha ;use stack to load status +152f : 28 > plp + +1530 : a0c3 ldy #$c3 +1532 : 08 php +1533 : cc1702 cpy abs1 ;test result + trap_ne +1536 : d0fe > bne * ;failed not equal (non zero) + +1538 : 68 pla ;load status + eor_flag 0 +1539 : 4930 > eor #0|fao ;invert expected flags + always on bits + +153b : cd1c02 cmp fLDx ;test flags + trap_ne +153e : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +1540 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1542 : 48 > pha ;use stack to load status +1543 : 28 > plp + +1544 : a082 ldy #$82 +1546 : 08 php +1547 : cc1802 cpy abs1+1 ;test result + trap_ne +154a : d0fe > bne * ;failed not equal (non zero) + +154c : 68 pla ;load status + eor_flag 0 +154d : 4930 > eor #0|fao ;invert expected flags + always on bits + +154f : cd1d02 cmp fLDx+1 ;test flags + trap_ne +1552 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +1554 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1556 : 48 > pha ;use stack to load status +1557 : 28 > plp + +1558 : a041 ldy #$41 +155a : 08 php +155b : cc1902 cpy abs1+2 ;test result + trap_ne +155e : d0fe > bne * ;failed not equal (non zero) + +1560 : 68 pla ;load status + eor_flag 0 +1561 : 4930 > eor #0|fao ;invert expected flags + always on bits + +1563 : cd1e02 cmp fLDx+2 ;test flags + trap_ne +1566 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +1568 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +156a : 48 > pha ;use stack to load status +156b : 28 > plp + +156c : a000 ldy #0 +156e : 08 php +156f : cc1a02 cpy abs1+3 ;test result + trap_ne +1572 : d0fe > bne * ;failed not equal (non zero) + +1574 : 68 pla ;load status + eor_flag 0 +1575 : 4930 > eor #0|fao ;invert expected flags + always on bits + +1577 : cd1f02 cmp fLDx+3 ;test flags + trap_ne +157a : d0fe > bne * ;failed not equal (non zero) + + + set_stat $ff + > load_flag $ff +157c : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +157e : 48 > pha ;use stack to load status +157f : 28 > plp + +1580 : a0c3 ldy #$c3 +1582 : 08 php +1583 : cc1702 cpy abs1 ;test result + trap_ne +1586 : d0fe > bne * ;failed not equal (non zero) + +1588 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +1589 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +158b : cd1c02 cmp fLDx ;test flags + trap_ne +158e : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +1590 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1592 : 48 > pha ;use stack to load status +1593 : 28 > plp + +1594 : a082 ldy #$82 +1596 : 08 php +1597 : cc1802 cpy abs1+1 ;test result + trap_ne +159a : d0fe > bne * ;failed not equal (non zero) + +159c : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +159d : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +159f : cd1d02 cmp fLDx+1 ;test flags + trap_ne +15a2 : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +15a4 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +15a6 : 48 > pha ;use stack to load status +15a7 : 28 > plp + +15a8 : a041 ldy #$41 +15aa : 08 php +15ab : cc1902 cpy abs1+2 ;test result + trap_ne +15ae : d0fe > bne * ;failed not equal (non zero) + +15b0 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +15b1 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +15b3 : cd1e02 cmp fLDx+2 ;test flags + trap_ne +15b6 : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +15b8 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +15ba : 48 > pha ;use stack to load status +15bb : 28 > plp + +15bc : a000 ldy #0 +15be : 08 php +15bf : cc1a02 cpy abs1+3 ;test result + trap_ne +15c2 : d0fe > bne * ;failed not equal (non zero) + +15c4 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +15c5 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +15c7 : cd1f02 cmp fLDx+3 ;test flags + trap_ne +15ca : d0fe > bne * ;failed not equal (non zero) + + +15cc : a000 ldy #0 +15ce : a50c lda zpt +15d0 : 49c3 eor #$c3 +15d2 : c513 cmp zp1 + trap_ne ;store to zp data +15d4 : d0fe > bne * ;failed not equal (non zero) + +15d6 : 840c sty zpt ;clear +15d8 : ad0302 lda abst +15db : 49c3 eor #$c3 +15dd : cd1702 cmp abs1 + trap_ne ;store to abs data +15e0 : d0fe > bne * ;failed not equal (non zero) + +15e2 : 8c0302 sty abst ;clear +15e5 : a50d lda zpt+1 +15e7 : 49c3 eor #$c3 +15e9 : c514 cmp zp1+1 + trap_ne ;store to zp+1 data +15eb : d0fe > bne * ;failed not equal (non zero) + +15ed : 840d sty zpt+1 ;clear +15ef : ad0402 lda abst+1 +15f2 : 49c3 eor #$c3 +15f4 : cd1802 cmp abs1+1 + trap_ne ;store to abs+1 data +15f7 : d0fe > bne * ;failed not equal (non zero) + +15f9 : 8c0402 sty abst+1 ;clear +15fc : a50e lda zpt+2 +15fe : 49c3 eor #$c3 +1600 : c515 cmp zp1+2 + trap_ne ;store to zp+2 data +1602 : d0fe > bne * ;failed not equal (non zero) + +1604 : 840e sty zpt+2 ;clear +1606 : ad0502 lda abst+2 +1609 : 49c3 eor #$c3 +160b : cd1902 cmp abs1+2 + trap_ne ;store to abs+2 data +160e : d0fe > bne * ;failed not equal (non zero) + +1610 : 8c0502 sty abst+2 ;clear +1613 : a50f lda zpt+3 +1615 : 49c3 eor #$c3 +1617 : c516 cmp zp1+3 + trap_ne ;store to zp+3 data +1619 : d0fe > bne * ;failed not equal (non zero) + +161b : 840f sty zpt+3 ;clear +161d : ad0602 lda abst+3 +1620 : 49c3 eor #$c3 +1622 : cd1a02 cmp abs1+3 + trap_ne ;store to abs+3 data +1625 : d0fe > bne * ;failed not equal (non zero) + +1627 : 8c0602 sty abst+3 ;clear + next_test +162a : ad0002 > lda test_case ;previous test +162d : c914 > cmp #test_num + > trap_ne ;test is out of sequence +162f : d0fe > bne * ;failed not equal (non zero) + > +0015 = >test_num = test_num + 1 +1631 : a915 > lda #test_num ;*** next tests' number +1633 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; testing load / store accumulator LDA / STA all addressing modes + ; LDA / STA - zp,x / abs,x +1636 : a203 ldx #3 +1638 : tldax + set_stat 0 + > load_flag 0 +1638 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +163a : 48 > pha ;use stack to load status +163b : 28 > plp + +163c : b513 lda zp1,x +163e : 08 php ;test stores do not alter flags +163f : 49c3 eor #$c3 +1641 : 28 plp +1642 : 9d0302 sta abst,x +1645 : 08 php ;flags after load/store sequence +1646 : 49c3 eor #$c3 +1648 : dd1702 cmp abs1,x ;test result + trap_ne +164b : d0fe > bne * ;failed not equal (non zero) + +164d : 68 pla ;load status + eor_flag 0 +164e : 4930 > eor #0|fao ;invert expected flags + always on bits + +1650 : dd1c02 cmp fLDx,x ;test flags + trap_ne +1653 : d0fe > bne * ;failed not equal (non zero) + +1655 : ca dex +1656 : 10e0 bpl tldax + +1658 : a203 ldx #3 +165a : tldax1 + set_stat $ff + > load_flag $ff +165a : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +165c : 48 > pha ;use stack to load status +165d : 28 > plp + +165e : b513 lda zp1,x +1660 : 08 php ;test stores do not alter flags +1661 : 49c3 eor #$c3 +1663 : 28 plp +1664 : 9d0302 sta abst,x +1667 : 08 php ;flags after load/store sequence +1668 : 49c3 eor #$c3 +166a : dd1702 cmp abs1,x ;test result + trap_ne +166d : d0fe > bne * ;failed not equal (non zero) + +166f : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +1670 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +1672 : dd1c02 cmp fLDx,x ;test flags + trap_ne +1675 : d0fe > bne * ;failed not equal (non zero) + +1677 : ca dex +1678 : 10e0 bpl tldax1 + +167a : a203 ldx #3 +167c : tldax2 + set_stat 0 + > load_flag 0 +167c : a900 > lda #0 ;allow test to change I-flag (no mask) + > +167e : 48 > pha ;use stack to load status +167f : 28 > plp + +1680 : bd1702 lda abs1,x +1683 : 08 php ;test stores do not alter flags +1684 : 49c3 eor #$c3 +1686 : 28 plp +1687 : 950c sta zpt,x +1689 : 08 php ;flags after load/store sequence +168a : 49c3 eor #$c3 +168c : d513 cmp zp1,x ;test result + trap_ne +168e : d0fe > bne * ;failed not equal (non zero) + +1690 : 68 pla ;load status + eor_flag 0 +1691 : 4930 > eor #0|fao ;invert expected flags + always on bits + +1693 : dd1c02 cmp fLDx,x ;test flags + trap_ne +1696 : d0fe > bne * ;failed not equal (non zero) + +1698 : ca dex +1699 : 10e1 bpl tldax2 + +169b : a203 ldx #3 +169d : tldax3 + set_stat $ff + > load_flag $ff +169d : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +169f : 48 > pha ;use stack to load status +16a0 : 28 > plp + +16a1 : bd1702 lda abs1,x +16a4 : 08 php ;test stores do not alter flags +16a5 : 49c3 eor #$c3 +16a7 : 28 plp +16a8 : 950c sta zpt,x +16aa : 08 php ;flags after load/store sequence +16ab : 49c3 eor #$c3 +16ad : d513 cmp zp1,x ;test result + trap_ne +16af : d0fe > bne * ;failed not equal (non zero) + +16b1 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +16b2 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +16b4 : dd1c02 cmp fLDx,x ;test flags + trap_ne +16b7 : d0fe > bne * ;failed not equal (non zero) + +16b9 : ca dex +16ba : 10e1 bpl tldax3 + +16bc : a203 ldx #3 ;testing store result +16be : a000 ldy #0 +16c0 : b50c tstax lda zpt,x +16c2 : 49c3 eor #$c3 +16c4 : d513 cmp zp1,x + trap_ne ;store to zp,x data +16c6 : d0fe > bne * ;failed not equal (non zero) + +16c8 : 940c sty zpt,x ;clear +16ca : bd0302 lda abst,x +16cd : 49c3 eor #$c3 +16cf : dd1702 cmp abs1,x + trap_ne ;store to abs,x data +16d2 : d0fe > bne * ;failed not equal (non zero) + +16d4 : 8a txa +16d5 : 9d0302 sta abst,x ;clear +16d8 : ca dex +16d9 : 10e5 bpl tstax + next_test +16db : ad0002 > lda test_case ;previous test +16de : c915 > cmp #test_num + > trap_ne ;test is out of sequence +16e0 : d0fe > bne * ;failed not equal (non zero) + > +0016 = >test_num = test_num + 1 +16e2 : a916 > lda #test_num ;*** next tests' number +16e4 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; LDA / STA - (zp),y / abs,y / (zp,x) +16e7 : a003 ldy #3 +16e9 : tlday + set_stat 0 + > load_flag 0 +16e9 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +16eb : 48 > pha ;use stack to load status +16ec : 28 > plp + +16ed : b124 lda (ind1),y +16ef : 08 php ;test stores do not alter flags +16f0 : 49c3 eor #$c3 +16f2 : 28 plp +16f3 : 990302 sta abst,y +16f6 : 08 php ;flags after load/store sequence +16f7 : 49c3 eor #$c3 +16f9 : d91702 cmp abs1,y ;test result + trap_ne +16fc : d0fe > bne * ;failed not equal (non zero) + +16fe : 68 pla ;load status + eor_flag 0 +16ff : 4930 > eor #0|fao ;invert expected flags + always on bits + +1701 : d91c02 cmp fLDx,y ;test flags + trap_ne +1704 : d0fe > bne * ;failed not equal (non zero) + +1706 : 88 dey +1707 : 10e0 bpl tlday + +1709 : a003 ldy #3 +170b : tlday1 + set_stat $ff + > load_flag $ff +170b : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +170d : 48 > pha ;use stack to load status +170e : 28 > plp + +170f : b124 lda (ind1),y +1711 : 08 php ;test stores do not alter flags +1712 : 49c3 eor #$c3 +1714 : 28 plp +1715 : 990302 sta abst,y +1718 : 08 php ;flags after load/store sequence +1719 : 49c3 eor #$c3 +171b : d91702 cmp abs1,y ;test result + trap_ne +171e : d0fe > bne * ;failed not equal (non zero) + +1720 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +1721 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +1723 : d91c02 cmp fLDx,y ;test flags + trap_ne +1726 : d0fe > bne * ;failed not equal (non zero) + +1728 : 88 dey +1729 : 10e0 bpl tlday1 + +172b : a003 ldy #3 ;testing store result +172d : a200 ldx #0 +172f : b90302 tstay lda abst,y +1732 : 49c3 eor #$c3 +1734 : d91702 cmp abs1,y + trap_ne ;store to abs data +1737 : d0fe > bne * ;failed not equal (non zero) + +1739 : 8a txa +173a : 990302 sta abst,y ;clear +173d : 88 dey +173e : 10ef bpl tstay + +1740 : a003 ldy #3 +1742 : tlday2 + set_stat 0 + > load_flag 0 +1742 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1744 : 48 > pha ;use stack to load status +1745 : 28 > plp + +1746 : b91702 lda abs1,y +1749 : 08 php ;test stores do not alter flags +174a : 49c3 eor #$c3 +174c : 28 plp +174d : 9130 sta (indt),y +174f : 08 php ;flags after load/store sequence +1750 : 49c3 eor #$c3 +1752 : d124 cmp (ind1),y ;test result + trap_ne +1754 : d0fe > bne * ;failed not equal (non zero) + +1756 : 68 pla ;load status + eor_flag 0 +1757 : 4930 > eor #0|fao ;invert expected flags + always on bits + +1759 : d91c02 cmp fLDx,y ;test flags + trap_ne +175c : d0fe > bne * ;failed not equal (non zero) + +175e : 88 dey +175f : 10e1 bpl tlday2 + +1761 : a003 ldy #3 +1763 : tlday3 + set_stat $ff + > load_flag $ff +1763 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1765 : 48 > pha ;use stack to load status +1766 : 28 > plp + +1767 : b91702 lda abs1,y +176a : 08 php ;test stores do not alter flags +176b : 49c3 eor #$c3 +176d : 28 plp +176e : 9130 sta (indt),y +1770 : 08 php ;flags after load/store sequence +1771 : 49c3 eor #$c3 +1773 : d124 cmp (ind1),y ;test result + trap_ne +1775 : d0fe > bne * ;failed not equal (non zero) + +1777 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +1778 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +177a : d91c02 cmp fLDx,y ;test flags + trap_ne +177d : d0fe > bne * ;failed not equal (non zero) + +177f : 88 dey +1780 : 10e1 bpl tlday3 + +1782 : a003 ldy #3 ;testing store result +1784 : a200 ldx #0 +1786 : b90302 tstay1 lda abst,y +1789 : 49c3 eor #$c3 +178b : d91702 cmp abs1,y + trap_ne ;store to abs data +178e : d0fe > bne * ;failed not equal (non zero) + +1790 : 8a txa +1791 : 990302 sta abst,y ;clear +1794 : 88 dey +1795 : 10ef bpl tstay1 + +1797 : a206 ldx #6 +1799 : a003 ldy #3 +179b : tldax4 + set_stat 0 + > load_flag 0 +179b : a900 > lda #0 ;allow test to change I-flag (no mask) + > +179d : 48 > pha ;use stack to load status +179e : 28 > plp + +179f : a124 lda (ind1,x) +17a1 : 08 php ;test stores do not alter flags +17a2 : 49c3 eor #$c3 +17a4 : 28 plp +17a5 : 8130 sta (indt,x) +17a7 : 08 php ;flags after load/store sequence +17a8 : 49c3 eor #$c3 +17aa : d91702 cmp abs1,y ;test result + trap_ne +17ad : d0fe > bne * ;failed not equal (non zero) + +17af : 68 pla ;load status + eor_flag 0 +17b0 : 4930 > eor #0|fao ;invert expected flags + always on bits + +17b2 : d91c02 cmp fLDx,y ;test flags + trap_ne +17b5 : d0fe > bne * ;failed not equal (non zero) + +17b7 : ca dex +17b8 : ca dex +17b9 : 88 dey +17ba : 10df bpl tldax4 + +17bc : a206 ldx #6 +17be : a003 ldy #3 +17c0 : tldax5 + set_stat $ff + > load_flag $ff +17c0 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +17c2 : 48 > pha ;use stack to load status +17c3 : 28 > plp + +17c4 : a124 lda (ind1,x) +17c6 : 08 php ;test stores do not alter flags +17c7 : 49c3 eor #$c3 +17c9 : 28 plp +17ca : 8130 sta (indt,x) +17cc : 08 php ;flags after load/store sequence +17cd : 49c3 eor #$c3 +17cf : d91702 cmp abs1,y ;test result + trap_ne +17d2 : d0fe > bne * ;failed not equal (non zero) + +17d4 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +17d5 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +17d7 : d91c02 cmp fLDx,y ;test flags + trap_ne +17da : d0fe > bne * ;failed not equal (non zero) + +17dc : ca dex +17dd : ca dex +17de : 88 dey +17df : 10df bpl tldax5 + +17e1 : a003 ldy #3 ;testing store result +17e3 : a200 ldx #0 +17e5 : b90302 tstay2 lda abst,y +17e8 : 49c3 eor #$c3 +17ea : d91702 cmp abs1,y + trap_ne ;store to abs data +17ed : d0fe > bne * ;failed not equal (non zero) + +17ef : 8a txa +17f0 : 990302 sta abst,y ;clear +17f3 : 88 dey +17f4 : 10ef bpl tstay2 + next_test +17f6 : ad0002 > lda test_case ;previous test +17f9 : c916 > cmp #test_num + > trap_ne ;test is out of sequence +17fb : d0fe > bne * ;failed not equal (non zero) + > +0017 = >test_num = test_num + 1 +17fd : a917 > lda #test_num ;*** next tests' number +17ff : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; indexed wraparound test (only zp should wrap) +1802 : a2fd ldx #3+$fa +1804 : b519 tldax6 lda zp1-$fa&$ff,x ;wrap on indexed zp +1806 : 9d0901 sta abst-$fa,x ;no STX abs,x! +1809 : ca dex +180a : e0fa cpx #$fa +180c : b0f6 bcs tldax6 +180e : a2fd ldx #3+$fa +1810 : bd1d01 tldax7 lda abs1-$fa,x ;no wrap on indexed abs +1813 : 9512 sta zpt-$fa&$ff,x +1815 : ca dex +1816 : e0fa cpx #$fa +1818 : b0f6 bcs tldax7 + +181a : a203 ldx #3 ;testing wraparound result +181c : a000 ldy #0 +181e : b50c tstax1 lda zpt,x +1820 : d513 cmp zp1,x + trap_ne ;store to zp,x data +1822 : d0fe > bne * ;failed not equal (non zero) + +1824 : 940c sty zpt,x ;clear +1826 : bd0302 lda abst,x +1829 : dd1702 cmp abs1,x + trap_ne ;store to abs,x data +182c : d0fe > bne * ;failed not equal (non zero) + +182e : 8a txa +182f : 9d0302 sta abst,x ;clear +1832 : ca dex +1833 : 10e9 bpl tstax1 + +1835 : a0fb ldy #3+$f8 +1837 : a2fe ldx #6+$f8 +1839 : a12c tlday4 lda (ind1-$f8&$ff,x) ;wrap on indexed zp indirect +183b : 990b01 sta abst-$f8,y +183e : ca dex +183f : ca dex +1840 : 88 dey +1841 : c0f8 cpy #$f8 +1843 : b0f4 bcs tlday4 +1845 : a003 ldy #3 ;testing wraparound result +1847 : a200 ldx #0 +1849 : b90302 tstay4 lda abst,y +184c : d91702 cmp abs1,y + trap_ne ;store to abs data +184f : d0fe > bne * ;failed not equal (non zero) + +1851 : 8a txa +1852 : 990302 sta abst,y ;clear +1855 : 88 dey +1856 : 10f1 bpl tstay4 + +1858 : a0fb ldy #3+$f8 +185a : b91f01 tlday5 lda abs1-$f8,y ;no wrap on indexed abs +185d : 9138 sta (inwt),y +185f : 88 dey +1860 : c0f8 cpy #$f8 +1862 : b0f6 bcs tlday5 +1864 : a003 ldy #3 ;testing wraparound result +1866 : a200 ldx #0 +1868 : b90302 tstay5 lda abst,y +186b : d91702 cmp abs1,y + trap_ne ;store to abs data +186e : d0fe > bne * ;failed not equal (non zero) + +1870 : 8a txa +1871 : 990302 sta abst,y ;clear +1874 : 88 dey +1875 : 10f1 bpl tstay5 + +1877 : a0fb ldy #3+$f8 +1879 : a2fe ldx #6+$f8 +187b : b12e tlday6 lda (inw1),y ;no wrap on zp indirect indexed +187d : 8138 sta (indt-$f8&$ff,x) +187f : ca dex +1880 : ca dex +1881 : 88 dey +1882 : c0f8 cpy #$f8 +1884 : b0f5 bcs tlday6 +1886 : a003 ldy #3 ;testing wraparound result +1888 : a200 ldx #0 +188a : b90302 tstay6 lda abst,y +188d : d91702 cmp abs1,y + trap_ne ;store to abs data +1890 : d0fe > bne * ;failed not equal (non zero) + +1892 : 8a txa +1893 : 990302 sta abst,y ;clear +1896 : 88 dey +1897 : 10f1 bpl tstay6 + next_test +1899 : ad0002 > lda test_case ;previous test +189c : c917 > cmp #test_num + > trap_ne ;test is out of sequence +189e : d0fe > bne * ;failed not equal (non zero) + > +0018 = >test_num = test_num + 1 +18a0 : a918 > lda #test_num ;*** next tests' number +18a2 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; LDA / STA - zp / abs / # + set_stat 0 + > load_flag 0 +18a5 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +18a7 : 48 > pha ;use stack to load status +18a8 : 28 > plp + +18a9 : a513 lda zp1 +18ab : 08 php ;test stores do not alter flags +18ac : 49c3 eor #$c3 +18ae : 28 plp +18af : 8d0302 sta abst +18b2 : 08 php ;flags after load/store sequence +18b3 : 49c3 eor #$c3 +18b5 : c9c3 cmp #$c3 ;test result + trap_ne +18b7 : d0fe > bne * ;failed not equal (non zero) + +18b9 : 68 pla ;load status + eor_flag 0 +18ba : 4930 > eor #0|fao ;invert expected flags + always on bits + +18bc : cd1c02 cmp fLDx ;test flags + trap_ne +18bf : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +18c1 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +18c3 : 48 > pha ;use stack to load status +18c4 : 28 > plp + +18c5 : a514 lda zp1+1 +18c7 : 08 php ;test stores do not alter flags +18c8 : 49c3 eor #$c3 +18ca : 28 plp +18cb : 8d0402 sta abst+1 +18ce : 08 php ;flags after load/store sequence +18cf : 49c3 eor #$c3 +18d1 : c982 cmp #$82 ;test result + trap_ne +18d3 : d0fe > bne * ;failed not equal (non zero) + +18d5 : 68 pla ;load status + eor_flag 0 +18d6 : 4930 > eor #0|fao ;invert expected flags + always on bits + +18d8 : cd1d02 cmp fLDx+1 ;test flags + trap_ne +18db : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +18dd : a900 > lda #0 ;allow test to change I-flag (no mask) + > +18df : 48 > pha ;use stack to load status +18e0 : 28 > plp + +18e1 : a515 lda zp1+2 +18e3 : 08 php ;test stores do not alter flags +18e4 : 49c3 eor #$c3 +18e6 : 28 plp +18e7 : 8d0502 sta abst+2 +18ea : 08 php ;flags after load/store sequence +18eb : 49c3 eor #$c3 +18ed : c941 cmp #$41 ;test result + trap_ne +18ef : d0fe > bne * ;failed not equal (non zero) + +18f1 : 68 pla ;load status + eor_flag 0 +18f2 : 4930 > eor #0|fao ;invert expected flags + always on bits + +18f4 : cd1e02 cmp fLDx+2 ;test flags + trap_ne +18f7 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +18f9 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +18fb : 48 > pha ;use stack to load status +18fc : 28 > plp + +18fd : a516 lda zp1+3 +18ff : 08 php ;test stores do not alter flags +1900 : 49c3 eor #$c3 +1902 : 28 plp +1903 : 8d0602 sta abst+3 +1906 : 08 php ;flags after load/store sequence +1907 : 49c3 eor #$c3 +1909 : c900 cmp #0 ;test result + trap_ne +190b : d0fe > bne * ;failed not equal (non zero) + +190d : 68 pla ;load status + eor_flag 0 +190e : 4930 > eor #0|fao ;invert expected flags + always on bits + +1910 : cd1f02 cmp fLDx+3 ;test flags + trap_ne +1913 : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +1915 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1917 : 48 > pha ;use stack to load status +1918 : 28 > plp + +1919 : a513 lda zp1 +191b : 08 php ;test stores do not alter flags +191c : 49c3 eor #$c3 +191e : 28 plp +191f : 8d0302 sta abst +1922 : 08 php ;flags after load/store sequence +1923 : 49c3 eor #$c3 +1925 : c9c3 cmp #$c3 ;test result + trap_ne +1927 : d0fe > bne * ;failed not equal (non zero) + +1929 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +192a : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +192c : cd1c02 cmp fLDx ;test flags + trap_ne +192f : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +1931 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1933 : 48 > pha ;use stack to load status +1934 : 28 > plp + +1935 : a514 lda zp1+1 +1937 : 08 php ;test stores do not alter flags +1938 : 49c3 eor #$c3 +193a : 28 plp +193b : 8d0402 sta abst+1 +193e : 08 php ;flags after load/store sequence +193f : 49c3 eor #$c3 +1941 : c982 cmp #$82 ;test result + trap_ne +1943 : d0fe > bne * ;failed not equal (non zero) + +1945 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +1946 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +1948 : cd1d02 cmp fLDx+1 ;test flags + trap_ne +194b : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +194d : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +194f : 48 > pha ;use stack to load status +1950 : 28 > plp + +1951 : a515 lda zp1+2 +1953 : 08 php ;test stores do not alter flags +1954 : 49c3 eor #$c3 +1956 : 28 plp +1957 : 8d0502 sta abst+2 +195a : 08 php ;flags after load/store sequence +195b : 49c3 eor #$c3 +195d : c941 cmp #$41 ;test result + trap_ne +195f : d0fe > bne * ;failed not equal (non zero) + +1961 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +1962 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +1964 : cd1e02 cmp fLDx+2 ;test flags + trap_ne +1967 : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +1969 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +196b : 48 > pha ;use stack to load status +196c : 28 > plp + +196d : a516 lda zp1+3 +196f : 08 php ;test stores do not alter flags +1970 : 49c3 eor #$c3 +1972 : 28 plp +1973 : 8d0602 sta abst+3 +1976 : 08 php ;flags after load/store sequence +1977 : 49c3 eor #$c3 +1979 : c900 cmp #0 ;test result + trap_ne +197b : d0fe > bne * ;failed not equal (non zero) + +197d : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +197e : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +1980 : cd1f02 cmp fLDx+3 ;test flags + trap_ne +1983 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +1985 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1987 : 48 > pha ;use stack to load status +1988 : 28 > plp + +1989 : ad1702 lda abs1 +198c : 08 php ;test stores do not alter flags +198d : 49c3 eor #$c3 +198f : 28 plp +1990 : 850c sta zpt +1992 : 08 php ;flags after load/store sequence +1993 : 49c3 eor #$c3 +1995 : c513 cmp zp1 ;test result + trap_ne +1997 : d0fe > bne * ;failed not equal (non zero) + +1999 : 68 pla ;load status + eor_flag 0 +199a : 4930 > eor #0|fao ;invert expected flags + always on bits + +199c : cd1c02 cmp fLDx ;test flags + trap_ne +199f : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +19a1 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +19a3 : 48 > pha ;use stack to load status +19a4 : 28 > plp + +19a5 : ad1802 lda abs1+1 +19a8 : 08 php ;test stores do not alter flags +19a9 : 49c3 eor #$c3 +19ab : 28 plp +19ac : 850d sta zpt+1 +19ae : 08 php ;flags after load/store sequence +19af : 49c3 eor #$c3 +19b1 : c514 cmp zp1+1 ;test result + trap_ne +19b3 : d0fe > bne * ;failed not equal (non zero) + +19b5 : 68 pla ;load status + eor_flag 0 +19b6 : 4930 > eor #0|fao ;invert expected flags + always on bits + +19b8 : cd1d02 cmp fLDx+1 ;test flags + trap_ne +19bb : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +19bd : a900 > lda #0 ;allow test to change I-flag (no mask) + > +19bf : 48 > pha ;use stack to load status +19c0 : 28 > plp + +19c1 : ad1902 lda abs1+2 +19c4 : 08 php ;test stores do not alter flags +19c5 : 49c3 eor #$c3 +19c7 : 28 plp +19c8 : 850e sta zpt+2 +19ca : 08 php ;flags after load/store sequence +19cb : 49c3 eor #$c3 +19cd : c515 cmp zp1+2 ;test result + trap_ne +19cf : d0fe > bne * ;failed not equal (non zero) + +19d1 : 68 pla ;load status + eor_flag 0 +19d2 : 4930 > eor #0|fao ;invert expected flags + always on bits + +19d4 : cd1e02 cmp fLDx+2 ;test flags + trap_ne +19d7 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +19d9 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +19db : 48 > pha ;use stack to load status +19dc : 28 > plp + +19dd : ad1a02 lda abs1+3 +19e0 : 08 php ;test stores do not alter flags +19e1 : 49c3 eor #$c3 +19e3 : 28 plp +19e4 : 850f sta zpt+3 +19e6 : 08 php ;flags after load/store sequence +19e7 : 49c3 eor #$c3 +19e9 : c516 cmp zp1+3 ;test result + trap_ne +19eb : d0fe > bne * ;failed not equal (non zero) + +19ed : 68 pla ;load status + eor_flag 0 +19ee : 4930 > eor #0|fao ;invert expected flags + always on bits + +19f0 : cd1f02 cmp fLDx+3 ;test flags + trap_ne +19f3 : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +19f5 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +19f7 : 48 > pha ;use stack to load status +19f8 : 28 > plp + +19f9 : ad1702 lda abs1 +19fc : 08 php ;test stores do not alter flags +19fd : 49c3 eor #$c3 +19ff : 28 plp +1a00 : 850c sta zpt +1a02 : 08 php ;flags after load/store sequence +1a03 : 49c3 eor #$c3 +1a05 : c513 cmp zp1 ;test result + trap_ne +1a07 : d0fe > bne * ;failed not equal (non zero) + +1a09 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +1a0a : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +1a0c : cd1c02 cmp fLDx ;test flags + trap_ne +1a0f : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +1a11 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1a13 : 48 > pha ;use stack to load status +1a14 : 28 > plp + +1a15 : ad1802 lda abs1+1 +1a18 : 08 php ;test stores do not alter flags +1a19 : 49c3 eor #$c3 +1a1b : 28 plp +1a1c : 850d sta zpt+1 +1a1e : 08 php ;flags after load/store sequence +1a1f : 49c3 eor #$c3 +1a21 : c514 cmp zp1+1 ;test result + trap_ne +1a23 : d0fe > bne * ;failed not equal (non zero) + +1a25 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +1a26 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +1a28 : cd1d02 cmp fLDx+1 ;test flags + trap_ne +1a2b : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +1a2d : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1a2f : 48 > pha ;use stack to load status +1a30 : 28 > plp + +1a31 : ad1902 lda abs1+2 +1a34 : 08 php ;test stores do not alter flags +1a35 : 49c3 eor #$c3 +1a37 : 28 plp +1a38 : 850e sta zpt+2 +1a3a : 08 php ;flags after load/store sequence +1a3b : 49c3 eor #$c3 +1a3d : c515 cmp zp1+2 ;test result + trap_ne +1a3f : d0fe > bne * ;failed not equal (non zero) + +1a41 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +1a42 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +1a44 : cd1e02 cmp fLDx+2 ;test flags + trap_ne +1a47 : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +1a49 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1a4b : 48 > pha ;use stack to load status +1a4c : 28 > plp + +1a4d : ad1a02 lda abs1+3 +1a50 : 08 php ;test stores do not alter flags +1a51 : 49c3 eor #$c3 +1a53 : 28 plp +1a54 : 850f sta zpt+3 +1a56 : 08 php ;flags after load/store sequence +1a57 : 49c3 eor #$c3 +1a59 : c516 cmp zp1+3 ;test result + trap_ne +1a5b : d0fe > bne * ;failed not equal (non zero) + +1a5d : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +1a5e : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +1a60 : cd1f02 cmp fLDx+3 ;test flags + trap_ne +1a63 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +1a65 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1a67 : 48 > pha ;use stack to load status +1a68 : 28 > plp + +1a69 : a9c3 lda #$c3 +1a6b : 08 php +1a6c : cd1702 cmp abs1 ;test result + trap_ne +1a6f : d0fe > bne * ;failed not equal (non zero) + +1a71 : 68 pla ;load status + eor_flag 0 +1a72 : 4930 > eor #0|fao ;invert expected flags + always on bits + +1a74 : cd1c02 cmp fLDx ;test flags + trap_ne +1a77 : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +1a79 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1a7b : 48 > pha ;use stack to load status +1a7c : 28 > plp + +1a7d : a982 lda #$82 +1a7f : 08 php +1a80 : cd1802 cmp abs1+1 ;test result + trap_ne +1a83 : d0fe > bne * ;failed not equal (non zero) + +1a85 : 68 pla ;load status + eor_flag 0 +1a86 : 4930 > eor #0|fao ;invert expected flags + always on bits + +1a88 : cd1d02 cmp fLDx+1 ;test flags + trap_ne +1a8b : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +1a8d : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1a8f : 48 > pha ;use stack to load status +1a90 : 28 > plp + +1a91 : a941 lda #$41 +1a93 : 08 php +1a94 : cd1902 cmp abs1+2 ;test result + trap_ne +1a97 : d0fe > bne * ;failed not equal (non zero) + +1a99 : 68 pla ;load status + eor_flag 0 +1a9a : 4930 > eor #0|fao ;invert expected flags + always on bits + +1a9c : cd1e02 cmp fLDx+2 ;test flags + trap_ne +1a9f : d0fe > bne * ;failed not equal (non zero) + + set_stat 0 + > load_flag 0 +1aa1 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1aa3 : 48 > pha ;use stack to load status +1aa4 : 28 > plp + +1aa5 : a900 lda #0 +1aa7 : 08 php +1aa8 : cd1a02 cmp abs1+3 ;test result + trap_ne +1aab : d0fe > bne * ;failed not equal (non zero) + +1aad : 68 pla ;load status + eor_flag 0 +1aae : 4930 > eor #0|fao ;invert expected flags + always on bits + +1ab0 : cd1f02 cmp fLDx+3 ;test flags + trap_ne +1ab3 : d0fe > bne * ;failed not equal (non zero) + + + set_stat $ff + > load_flag $ff +1ab5 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1ab7 : 48 > pha ;use stack to load status +1ab8 : 28 > plp + +1ab9 : a9c3 lda #$c3 +1abb : 08 php +1abc : cd1702 cmp abs1 ;test result + trap_ne +1abf : d0fe > bne * ;failed not equal (non zero) + +1ac1 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +1ac2 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +1ac4 : cd1c02 cmp fLDx ;test flags + trap_ne +1ac7 : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +1ac9 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1acb : 48 > pha ;use stack to load status +1acc : 28 > plp + +1acd : a982 lda #$82 +1acf : 08 php +1ad0 : cd1802 cmp abs1+1 ;test result + trap_ne +1ad3 : d0fe > bne * ;failed not equal (non zero) + +1ad5 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +1ad6 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +1ad8 : cd1d02 cmp fLDx+1 ;test flags + trap_ne +1adb : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +1add : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1adf : 48 > pha ;use stack to load status +1ae0 : 28 > plp + +1ae1 : a941 lda #$41 +1ae3 : 08 php +1ae4 : cd1902 cmp abs1+2 ;test result + trap_ne +1ae7 : d0fe > bne * ;failed not equal (non zero) + +1ae9 : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +1aea : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +1aec : cd1e02 cmp fLDx+2 ;test flags + trap_ne +1aef : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +1af1 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1af3 : 48 > pha ;use stack to load status +1af4 : 28 > plp + +1af5 : a900 lda #0 +1af7 : 08 php +1af8 : cd1a02 cmp abs1+3 ;test result + trap_ne +1afb : d0fe > bne * ;failed not equal (non zero) + +1afd : 68 pla ;load status + eor_flag lo~fnz ;mask bits not altered +1afe : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits + +1b00 : cd1f02 cmp fLDx+3 ;test flags + trap_ne +1b03 : d0fe > bne * ;failed not equal (non zero) + + +1b05 : a200 ldx #0 +1b07 : a50c lda zpt +1b09 : 49c3 eor #$c3 +1b0b : c513 cmp zp1 + trap_ne ;store to zp data +1b0d : d0fe > bne * ;failed not equal (non zero) + +1b0f : 860c stx zpt ;clear +1b11 : ad0302 lda abst +1b14 : 49c3 eor #$c3 +1b16 : cd1702 cmp abs1 + trap_ne ;store to abs data +1b19 : d0fe > bne * ;failed not equal (non zero) + +1b1b : 8e0302 stx abst ;clear +1b1e : a50d lda zpt+1 +1b20 : 49c3 eor #$c3 +1b22 : c514 cmp zp1+1 + trap_ne ;store to zp data +1b24 : d0fe > bne * ;failed not equal (non zero) + +1b26 : 860d stx zpt+1 ;clear +1b28 : ad0402 lda abst+1 +1b2b : 49c3 eor #$c3 +1b2d : cd1802 cmp abs1+1 + trap_ne ;store to abs data +1b30 : d0fe > bne * ;failed not equal (non zero) + +1b32 : 8e0402 stx abst+1 ;clear +1b35 : a50e lda zpt+2 +1b37 : 49c3 eor #$c3 +1b39 : c515 cmp zp1+2 + trap_ne ;store to zp data +1b3b : d0fe > bne * ;failed not equal (non zero) + +1b3d : 860e stx zpt+2 ;clear +1b3f : ad0502 lda abst+2 +1b42 : 49c3 eor #$c3 +1b44 : cd1902 cmp abs1+2 + trap_ne ;store to abs data +1b47 : d0fe > bne * ;failed not equal (non zero) + +1b49 : 8e0502 stx abst+2 ;clear +1b4c : a50f lda zpt+3 +1b4e : 49c3 eor #$c3 +1b50 : c516 cmp zp1+3 + trap_ne ;store to zp data +1b52 : d0fe > bne * ;failed not equal (non zero) + +1b54 : 860f stx zpt+3 ;clear +1b56 : ad0602 lda abst+3 +1b59 : 49c3 eor #$c3 +1b5b : cd1a02 cmp abs1+3 + trap_ne ;store to abs data +1b5e : d0fe > bne * ;failed not equal (non zero) + +1b60 : 8e0602 stx abst+3 ;clear + next_test +1b63 : ad0002 > lda test_case ;previous test +1b66 : c918 > cmp #test_num + > trap_ne ;test is out of sequence +1b68 : d0fe > bne * ;failed not equal (non zero) + > +0019 = >test_num = test_num + 1 +1b6a : a919 > lda #test_num ;*** next tests' number +1b6c : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; testing bit test & compares BIT CPX CPY CMP all addressing modes + ; BIT - zp / abs + set_a $ff,0 + > load_flag 0 +1b6f : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1b71 : 48 > pha ;use stack to load status +1b72 : a9ff > lda #$ff ;precharge accu +1b74 : 28 > plp + +1b75 : 2416 bit zp1+3 ;00 - should set Z / clear NV + tst_a $ff,fz +1b77 : 08 > php ;save flags +1b78 : c9ff > cmp #$ff ;test result + > trap_ne +1b7a : d0fe > bne * ;failed not equal (non zero) + > +1b7c : 68 > pla ;load status +1b7d : 48 > pha + > cmp_flag fz +1b7e : c932 > cmp #(fz |fao)&m8 ;expected flags + always on bits + > + > trap_ne +1b80 : d0fe > bne * ;failed not equal (non zero) + > +1b82 : 28 > plp ;restore status + + set_a 1,0 + > load_flag 0 +1b83 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1b85 : 48 > pha ;use stack to load status +1b86 : a901 > lda #1 ;precharge accu +1b88 : 28 > plp + +1b89 : 2415 bit zp1+2 ;41 - should set V (M6) / clear NZ + tst_a 1,fv +1b8b : 08 > php ;save flags +1b8c : c901 > cmp #1 ;test result + > trap_ne +1b8e : d0fe > bne * ;failed not equal (non zero) + > +1b90 : 68 > pla ;load status +1b91 : 48 > pha + > cmp_flag fv +1b92 : c970 > cmp #(fv|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1b94 : d0fe > bne * ;failed not equal (non zero) + > +1b96 : 28 > plp ;restore status + + set_a 1,0 + > load_flag 0 +1b97 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1b99 : 48 > pha ;use stack to load status +1b9a : a901 > lda #1 ;precharge accu +1b9c : 28 > plp + +1b9d : 2414 bit zp1+1 ;82 - should set N (M7) & Z / clear V + tst_a 1,fnz +1b9f : 08 > php ;save flags +1ba0 : c901 > cmp #1 ;test result + > trap_ne +1ba2 : d0fe > bne * ;failed not equal (non zero) + > +1ba4 : 68 > pla ;load status +1ba5 : 48 > pha + > cmp_flag fnz +1ba6 : c9b2 > cmp #(fnz|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1ba8 : d0fe > bne * ;failed not equal (non zero) + > +1baa : 28 > plp ;restore status + + set_a 1,0 + > load_flag 0 +1bab : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1bad : 48 > pha ;use stack to load status +1bae : a901 > lda #1 ;precharge accu +1bb0 : 28 > plp + +1bb1 : 2413 bit zp1 ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,fnv +1bb3 : 08 > php ;save flags +1bb4 : c901 > cmp #1 ;test result + > trap_ne +1bb6 : d0fe > bne * ;failed not equal (non zero) + > +1bb8 : 68 > pla ;load status +1bb9 : 48 > pha + > cmp_flag fnv +1bba : c9f0 > cmp #(fnv|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1bbc : d0fe > bne * ;failed not equal (non zero) + > +1bbe : 28 > plp ;restore status + + + set_a $ff,$ff + > load_flag $ff +1bbf : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1bc1 : 48 > pha ;use stack to load status +1bc2 : a9ff > lda #$ff ;precharge accu +1bc4 : 28 > plp + +1bc5 : 2416 bit zp1+3 ;00 - should set Z / clear NV + tst_a $ff,~fnv +1bc7 : 08 > php ;save flags +1bc8 : c9ff > cmp #$ff ;test result + > trap_ne +1bca : d0fe > bne * ;failed not equal (non zero) + > +1bcc : 68 > pla ;load status +1bcd : 48 > pha + > cmp_flag ~fnv +1bce : c93f > cmp #(~fnv |fao)&m8 ;expected flags + always on bits + > + > trap_ne +1bd0 : d0fe > bne * ;failed not equal (non zero) + > +1bd2 : 28 > plp ;restore status + + set_a 1,$ff + > load_flag $ff +1bd3 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1bd5 : 48 > pha ;use stack to load status +1bd6 : a901 > lda #1 ;precharge accu +1bd8 : 28 > plp + +1bd9 : 2415 bit zp1+2 ;41 - should set V (M6) / clear NZ + tst_a 1,~fnz +1bdb : 08 > php ;save flags +1bdc : c901 > cmp #1 ;test result + > trap_ne +1bde : d0fe > bne * ;failed not equal (non zero) + > +1be0 : 68 > pla ;load status +1be1 : 48 > pha + > cmp_flag ~fnz +1be2 : c97d > cmp #(~fnz|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1be4 : d0fe > bne * ;failed not equal (non zero) + > +1be6 : 28 > plp ;restore status + + set_a 1,$ff + > load_flag $ff +1be7 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1be9 : 48 > pha ;use stack to load status +1bea : a901 > lda #1 ;precharge accu +1bec : 28 > plp + +1bed : 2414 bit zp1+1 ;82 - should set N (M7) & Z / clear V + tst_a 1,~fv +1bef : 08 > php ;save flags +1bf0 : c901 > cmp #1 ;test result + > trap_ne +1bf2 : d0fe > bne * ;failed not equal (non zero) + > +1bf4 : 68 > pla ;load status +1bf5 : 48 > pha + > cmp_flag ~fv +1bf6 : c9bf > cmp #(~fv|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1bf8 : d0fe > bne * ;failed not equal (non zero) + > +1bfa : 28 > plp ;restore status + + set_a 1,$ff + > load_flag $ff +1bfb : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1bfd : 48 > pha ;use stack to load status +1bfe : a901 > lda #1 ;precharge accu +1c00 : 28 > plp + +1c01 : 2413 bit zp1 ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,~fz +1c03 : 08 > php ;save flags +1c04 : c901 > cmp #1 ;test result + > trap_ne +1c06 : d0fe > bne * ;failed not equal (non zero) + > +1c08 : 68 > pla ;load status +1c09 : 48 > pha + > cmp_flag ~fz +1c0a : c9fd > cmp #(~fz|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1c0c : d0fe > bne * ;failed not equal (non zero) + > +1c0e : 28 > plp ;restore status + + + set_a $ff,0 + > load_flag 0 +1c0f : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1c11 : 48 > pha ;use stack to load status +1c12 : a9ff > lda #$ff ;precharge accu +1c14 : 28 > plp + +1c15 : 2c1a02 bit abs1+3 ;00 - should set Z / clear NV + tst_a $ff,fz +1c18 : 08 > php ;save flags +1c19 : c9ff > cmp #$ff ;test result + > trap_ne +1c1b : d0fe > bne * ;failed not equal (non zero) + > +1c1d : 68 > pla ;load status +1c1e : 48 > pha + > cmp_flag fz +1c1f : c932 > cmp #(fz |fao)&m8 ;expected flags + always on bits + > + > trap_ne +1c21 : d0fe > bne * ;failed not equal (non zero) + > +1c23 : 28 > plp ;restore status + + set_a 1,0 + > load_flag 0 +1c24 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1c26 : 48 > pha ;use stack to load status +1c27 : a901 > lda #1 ;precharge accu +1c29 : 28 > plp + +1c2a : 2c1902 bit abs1+2 ;41 - should set V (M6) / clear NZ + tst_a 1,fv +1c2d : 08 > php ;save flags +1c2e : c901 > cmp #1 ;test result + > trap_ne +1c30 : d0fe > bne * ;failed not equal (non zero) + > +1c32 : 68 > pla ;load status +1c33 : 48 > pha + > cmp_flag fv +1c34 : c970 > cmp #(fv|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1c36 : d0fe > bne * ;failed not equal (non zero) + > +1c38 : 28 > plp ;restore status + + set_a 1,0 + > load_flag 0 +1c39 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1c3b : 48 > pha ;use stack to load status +1c3c : a901 > lda #1 ;precharge accu +1c3e : 28 > plp + +1c3f : 2c1802 bit abs1+1 ;82 - should set N (M7) & Z / clear V + tst_a 1,fnz +1c42 : 08 > php ;save flags +1c43 : c901 > cmp #1 ;test result + > trap_ne +1c45 : d0fe > bne * ;failed not equal (non zero) + > +1c47 : 68 > pla ;load status +1c48 : 48 > pha + > cmp_flag fnz +1c49 : c9b2 > cmp #(fnz|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1c4b : d0fe > bne * ;failed not equal (non zero) + > +1c4d : 28 > plp ;restore status + + set_a 1,0 + > load_flag 0 +1c4e : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1c50 : 48 > pha ;use stack to load status +1c51 : a901 > lda #1 ;precharge accu +1c53 : 28 > plp + +1c54 : 2c1702 bit abs1 ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,fnv +1c57 : 08 > php ;save flags +1c58 : c901 > cmp #1 ;test result + > trap_ne +1c5a : d0fe > bne * ;failed not equal (non zero) + > +1c5c : 68 > pla ;load status +1c5d : 48 > pha + > cmp_flag fnv +1c5e : c9f0 > cmp #(fnv|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1c60 : d0fe > bne * ;failed not equal (non zero) + > +1c62 : 28 > plp ;restore status + + + set_a $ff,$ff + > load_flag $ff +1c63 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1c65 : 48 > pha ;use stack to load status +1c66 : a9ff > lda #$ff ;precharge accu +1c68 : 28 > plp + +1c69 : 2c1a02 bit abs1+3 ;00 - should set Z / clear NV + tst_a $ff,~fnv +1c6c : 08 > php ;save flags +1c6d : c9ff > cmp #$ff ;test result + > trap_ne +1c6f : d0fe > bne * ;failed not equal (non zero) + > +1c71 : 68 > pla ;load status +1c72 : 48 > pha + > cmp_flag ~fnv +1c73 : c93f > cmp #(~fnv |fao)&m8 ;expected flags + always on bits + > + > trap_ne +1c75 : d0fe > bne * ;failed not equal (non zero) + > +1c77 : 28 > plp ;restore status + + set_a 1,$ff + > load_flag $ff +1c78 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1c7a : 48 > pha ;use stack to load status +1c7b : a901 > lda #1 ;precharge accu +1c7d : 28 > plp + +1c7e : 2c1902 bit abs1+2 ;41 - should set V (M6) / clear NZ + tst_a 1,~fnz +1c81 : 08 > php ;save flags +1c82 : c901 > cmp #1 ;test result + > trap_ne +1c84 : d0fe > bne * ;failed not equal (non zero) + > +1c86 : 68 > pla ;load status +1c87 : 48 > pha + > cmp_flag ~fnz +1c88 : c97d > cmp #(~fnz|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1c8a : d0fe > bne * ;failed not equal (non zero) + > +1c8c : 28 > plp ;restore status + + set_a 1,$ff + > load_flag $ff +1c8d : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1c8f : 48 > pha ;use stack to load status +1c90 : a901 > lda #1 ;precharge accu +1c92 : 28 > plp + +1c93 : 2c1802 bit abs1+1 ;82 - should set N (M7) & Z / clear V + tst_a 1,~fv +1c96 : 08 > php ;save flags +1c97 : c901 > cmp #1 ;test result + > trap_ne +1c99 : d0fe > bne * ;failed not equal (non zero) + > +1c9b : 68 > pla ;load status +1c9c : 48 > pha + > cmp_flag ~fv +1c9d : c9bf > cmp #(~fv|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1c9f : d0fe > bne * ;failed not equal (non zero) + > +1ca1 : 28 > plp ;restore status + + set_a 1,$ff + > load_flag $ff +1ca2 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1ca4 : 48 > pha ;use stack to load status +1ca5 : a901 > lda #1 ;precharge accu +1ca7 : 28 > plp + +1ca8 : 2c1702 bit abs1 ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,~fz +1cab : 08 > php ;save flags +1cac : c901 > cmp #1 ;test result + > trap_ne +1cae : d0fe > bne * ;failed not equal (non zero) + > +1cb0 : 68 > pla ;load status +1cb1 : 48 > pha + > cmp_flag ~fz +1cb2 : c9fd > cmp #(~fz|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1cb4 : d0fe > bne * ;failed not equal (non zero) + > +1cb6 : 28 > plp ;restore status + + next_test +1cb7 : ad0002 > lda test_case ;previous test +1cba : c919 > cmp #test_num + > trap_ne ;test is out of sequence +1cbc : d0fe > bne * ;failed not equal (non zero) + > +001a = >test_num = test_num + 1 +1cbe : a91a > lda #test_num ;*** next tests' number +1cc0 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; CPX - zp / abs / # + set_x $80,0 + > load_flag 0 +1cc3 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1cc5 : 48 > pha ;use stack to load status +1cc6 : a280 > ldx #$80 ;precharge index x +1cc8 : 28 > plp + +1cc9 : e417 cpx zp7f + tst_stat fc +1ccb : 08 > php ;save status +1ccc : 68 > pla ;use stack to retrieve status +1ccd : 48 > pha + > cmp_flag fc +1cce : c931 > cmp #(fc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1cd0 : d0fe > bne * ;failed not equal (non zero) + > +1cd2 : 28 > plp ;restore status + +1cd3 : ca dex +1cd4 : e417 cpx zp7f + tst_stat fzc +1cd6 : 08 > php ;save status +1cd7 : 68 > pla ;use stack to retrieve status +1cd8 : 48 > pha + > cmp_flag fzc +1cd9 : c933 > cmp #(fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1cdb : d0fe > bne * ;failed not equal (non zero) + > +1cdd : 28 > plp ;restore status + +1cde : ca dex +1cdf : e417 cpx zp7f + tst_x $7e,fn +1ce1 : 08 > php ;save flags +1ce2 : e07e > cpx #$7e ;test result + > trap_ne +1ce4 : d0fe > bne * ;failed not equal (non zero) + > +1ce6 : 68 > pla ;load status +1ce7 : 48 > pha + > cmp_flag fn +1ce8 : c9b0 > cmp #(fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1cea : d0fe > bne * ;failed not equal (non zero) + > +1cec : 28 > plp ;restore status + + set_x $80,$ff + > load_flag $ff +1ced : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1cef : 48 > pha ;use stack to load status +1cf0 : a280 > ldx #$80 ;precharge index x +1cf2 : 28 > plp + +1cf3 : e417 cpx zp7f + tst_stat ~fnz +1cf5 : 08 > php ;save status +1cf6 : 68 > pla ;use stack to retrieve status +1cf7 : 48 > pha + > cmp_flag ~fnz +1cf8 : c97d > cmp #(~fnz|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1cfa : d0fe > bne * ;failed not equal (non zero) + > +1cfc : 28 > plp ;restore status + +1cfd : ca dex +1cfe : e417 cpx zp7f + tst_stat ~fn +1d00 : 08 > php ;save status +1d01 : 68 > pla ;use stack to retrieve status +1d02 : 48 > pha + > cmp_flag ~fn +1d03 : c97f > cmp #(~fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1d05 : d0fe > bne * ;failed not equal (non zero) + > +1d07 : 28 > plp ;restore status + +1d08 : ca dex +1d09 : e417 cpx zp7f + tst_x $7e,~fzc +1d0b : 08 > php ;save flags +1d0c : e07e > cpx #$7e ;test result + > trap_ne +1d0e : d0fe > bne * ;failed not equal (non zero) + > +1d10 : 68 > pla ;load status +1d11 : 48 > pha + > cmp_flag ~fzc +1d12 : c9fc > cmp #(~fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1d14 : d0fe > bne * ;failed not equal (non zero) + > +1d16 : 28 > plp ;restore status + + + set_x $80,0 + > load_flag 0 +1d17 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1d19 : 48 > pha ;use stack to load status +1d1a : a280 > ldx #$80 ;precharge index x +1d1c : 28 > plp + +1d1d : ec1b02 cpx abs7f + tst_stat fc +1d20 : 08 > php ;save status +1d21 : 68 > pla ;use stack to retrieve status +1d22 : 48 > pha + > cmp_flag fc +1d23 : c931 > cmp #(fc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1d25 : d0fe > bne * ;failed not equal (non zero) + > +1d27 : 28 > plp ;restore status + +1d28 : ca dex +1d29 : ec1b02 cpx abs7f + tst_stat fzc +1d2c : 08 > php ;save status +1d2d : 68 > pla ;use stack to retrieve status +1d2e : 48 > pha + > cmp_flag fzc +1d2f : c933 > cmp #(fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1d31 : d0fe > bne * ;failed not equal (non zero) + > +1d33 : 28 > plp ;restore status + +1d34 : ca dex +1d35 : ec1b02 cpx abs7f + tst_x $7e,fn +1d38 : 08 > php ;save flags +1d39 : e07e > cpx #$7e ;test result + > trap_ne +1d3b : d0fe > bne * ;failed not equal (non zero) + > +1d3d : 68 > pla ;load status +1d3e : 48 > pha + > cmp_flag fn +1d3f : c9b0 > cmp #(fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1d41 : d0fe > bne * ;failed not equal (non zero) + > +1d43 : 28 > plp ;restore status + + set_x $80,$ff + > load_flag $ff +1d44 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1d46 : 48 > pha ;use stack to load status +1d47 : a280 > ldx #$80 ;precharge index x +1d49 : 28 > plp + +1d4a : ec1b02 cpx abs7f + tst_stat ~fnz +1d4d : 08 > php ;save status +1d4e : 68 > pla ;use stack to retrieve status +1d4f : 48 > pha + > cmp_flag ~fnz +1d50 : c97d > cmp #(~fnz|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1d52 : d0fe > bne * ;failed not equal (non zero) + > +1d54 : 28 > plp ;restore status + +1d55 : ca dex +1d56 : ec1b02 cpx abs7f + tst_stat ~fn +1d59 : 08 > php ;save status +1d5a : 68 > pla ;use stack to retrieve status +1d5b : 48 > pha + > cmp_flag ~fn +1d5c : c97f > cmp #(~fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1d5e : d0fe > bne * ;failed not equal (non zero) + > +1d60 : 28 > plp ;restore status + +1d61 : ca dex +1d62 : ec1b02 cpx abs7f + tst_x $7e,~fzc +1d65 : 08 > php ;save flags +1d66 : e07e > cpx #$7e ;test result + > trap_ne +1d68 : d0fe > bne * ;failed not equal (non zero) + > +1d6a : 68 > pla ;load status +1d6b : 48 > pha + > cmp_flag ~fzc +1d6c : c9fc > cmp #(~fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1d6e : d0fe > bne * ;failed not equal (non zero) + > +1d70 : 28 > plp ;restore status + + + set_x $80,0 + > load_flag 0 +1d71 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1d73 : 48 > pha ;use stack to load status +1d74 : a280 > ldx #$80 ;precharge index x +1d76 : 28 > plp + +1d77 : e07f cpx #$7f + tst_stat fc +1d79 : 08 > php ;save status +1d7a : 68 > pla ;use stack to retrieve status +1d7b : 48 > pha + > cmp_flag fc +1d7c : c931 > cmp #(fc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1d7e : d0fe > bne * ;failed not equal (non zero) + > +1d80 : 28 > plp ;restore status + +1d81 : ca dex +1d82 : e07f cpx #$7f + tst_stat fzc +1d84 : 08 > php ;save status +1d85 : 68 > pla ;use stack to retrieve status +1d86 : 48 > pha + > cmp_flag fzc +1d87 : c933 > cmp #(fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1d89 : d0fe > bne * ;failed not equal (non zero) + > +1d8b : 28 > plp ;restore status + +1d8c : ca dex +1d8d : e07f cpx #$7f + tst_x $7e,fn +1d8f : 08 > php ;save flags +1d90 : e07e > cpx #$7e ;test result + > trap_ne +1d92 : d0fe > bne * ;failed not equal (non zero) + > +1d94 : 68 > pla ;load status +1d95 : 48 > pha + > cmp_flag fn +1d96 : c9b0 > cmp #(fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1d98 : d0fe > bne * ;failed not equal (non zero) + > +1d9a : 28 > plp ;restore status + + set_x $80,$ff + > load_flag $ff +1d9b : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1d9d : 48 > pha ;use stack to load status +1d9e : a280 > ldx #$80 ;precharge index x +1da0 : 28 > plp + +1da1 : e07f cpx #$7f + tst_stat ~fnz +1da3 : 08 > php ;save status +1da4 : 68 > pla ;use stack to retrieve status +1da5 : 48 > pha + > cmp_flag ~fnz +1da6 : c97d > cmp #(~fnz|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1da8 : d0fe > bne * ;failed not equal (non zero) + > +1daa : 28 > plp ;restore status + +1dab : ca dex +1dac : e07f cpx #$7f + tst_stat ~fn +1dae : 08 > php ;save status +1daf : 68 > pla ;use stack to retrieve status +1db0 : 48 > pha + > cmp_flag ~fn +1db1 : c97f > cmp #(~fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1db3 : d0fe > bne * ;failed not equal (non zero) + > +1db5 : 28 > plp ;restore status + +1db6 : ca dex +1db7 : e07f cpx #$7f + tst_x $7e,~fzc +1db9 : 08 > php ;save flags +1dba : e07e > cpx #$7e ;test result + > trap_ne +1dbc : d0fe > bne * ;failed not equal (non zero) + > +1dbe : 68 > pla ;load status +1dbf : 48 > pha + > cmp_flag ~fzc +1dc0 : c9fc > cmp #(~fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1dc2 : d0fe > bne * ;failed not equal (non zero) + > +1dc4 : 28 > plp ;restore status + + next_test +1dc5 : ad0002 > lda test_case ;previous test +1dc8 : c91a > cmp #test_num + > trap_ne ;test is out of sequence +1dca : d0fe > bne * ;failed not equal (non zero) + > +001b = >test_num = test_num + 1 +1dcc : a91b > lda #test_num ;*** next tests' number +1dce : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; CPY - zp / abs / # + set_y $80,0 + > load_flag 0 +1dd1 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1dd3 : 48 > pha ;use stack to load status +1dd4 : a080 > ldy #$80 ;precharge index y +1dd6 : 28 > plp + +1dd7 : c417 cpy zp7f + tst_stat fc +1dd9 : 08 > php ;save status +1dda : 68 > pla ;use stack to retrieve status +1ddb : 48 > pha + > cmp_flag fc +1ddc : c931 > cmp #(fc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1dde : d0fe > bne * ;failed not equal (non zero) + > +1de0 : 28 > plp ;restore status + +1de1 : 88 dey +1de2 : c417 cpy zp7f + tst_stat fzc +1de4 : 08 > php ;save status +1de5 : 68 > pla ;use stack to retrieve status +1de6 : 48 > pha + > cmp_flag fzc +1de7 : c933 > cmp #(fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1de9 : d0fe > bne * ;failed not equal (non zero) + > +1deb : 28 > plp ;restore status + +1dec : 88 dey +1ded : c417 cpy zp7f + tst_y $7e,fn +1def : 08 > php ;save flags +1df0 : c07e > cpy #$7e ;test result + > trap_ne +1df2 : d0fe > bne * ;failed not equal (non zero) + > +1df4 : 68 > pla ;load status +1df5 : 48 > pha + > cmp_flag fn +1df6 : c9b0 > cmp #(fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1df8 : d0fe > bne * ;failed not equal (non zero) + > +1dfa : 28 > plp ;restore status + + set_y $80,$ff + > load_flag $ff +1dfb : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1dfd : 48 > pha ;use stack to load status +1dfe : a080 > ldy #$80 ;precharge index y +1e00 : 28 > plp + +1e01 : c417 cpy zp7f + tst_stat ~fnz +1e03 : 08 > php ;save status +1e04 : 68 > pla ;use stack to retrieve status +1e05 : 48 > pha + > cmp_flag ~fnz +1e06 : c97d > cmp #(~fnz|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1e08 : d0fe > bne * ;failed not equal (non zero) + > +1e0a : 28 > plp ;restore status + +1e0b : 88 dey +1e0c : c417 cpy zp7f + tst_stat ~fn +1e0e : 08 > php ;save status +1e0f : 68 > pla ;use stack to retrieve status +1e10 : 48 > pha + > cmp_flag ~fn +1e11 : c97f > cmp #(~fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1e13 : d0fe > bne * ;failed not equal (non zero) + > +1e15 : 28 > plp ;restore status + +1e16 : 88 dey +1e17 : c417 cpy zp7f + tst_y $7e,~fzc +1e19 : 08 > php ;save flags +1e1a : c07e > cpy #$7e ;test result + > trap_ne +1e1c : d0fe > bne * ;failed not equal (non zero) + > +1e1e : 68 > pla ;load status +1e1f : 48 > pha + > cmp_flag ~fzc +1e20 : c9fc > cmp #(~fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1e22 : d0fe > bne * ;failed not equal (non zero) + > +1e24 : 28 > plp ;restore status + + + set_y $80,0 + > load_flag 0 +1e25 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1e27 : 48 > pha ;use stack to load status +1e28 : a080 > ldy #$80 ;precharge index y +1e2a : 28 > plp + +1e2b : cc1b02 cpy abs7f + tst_stat fc +1e2e : 08 > php ;save status +1e2f : 68 > pla ;use stack to retrieve status +1e30 : 48 > pha + > cmp_flag fc +1e31 : c931 > cmp #(fc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1e33 : d0fe > bne * ;failed not equal (non zero) + > +1e35 : 28 > plp ;restore status + +1e36 : 88 dey +1e37 : cc1b02 cpy abs7f + tst_stat fzc +1e3a : 08 > php ;save status +1e3b : 68 > pla ;use stack to retrieve status +1e3c : 48 > pha + > cmp_flag fzc +1e3d : c933 > cmp #(fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1e3f : d0fe > bne * ;failed not equal (non zero) + > +1e41 : 28 > plp ;restore status + +1e42 : 88 dey +1e43 : cc1b02 cpy abs7f + tst_y $7e,fn +1e46 : 08 > php ;save flags +1e47 : c07e > cpy #$7e ;test result + > trap_ne +1e49 : d0fe > bne * ;failed not equal (non zero) + > +1e4b : 68 > pla ;load status +1e4c : 48 > pha + > cmp_flag fn +1e4d : c9b0 > cmp #(fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1e4f : d0fe > bne * ;failed not equal (non zero) + > +1e51 : 28 > plp ;restore status + + set_y $80,$ff + > load_flag $ff +1e52 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1e54 : 48 > pha ;use stack to load status +1e55 : a080 > ldy #$80 ;precharge index y +1e57 : 28 > plp + +1e58 : cc1b02 cpy abs7f + tst_stat ~fnz +1e5b : 08 > php ;save status +1e5c : 68 > pla ;use stack to retrieve status +1e5d : 48 > pha + > cmp_flag ~fnz +1e5e : c97d > cmp #(~fnz|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1e60 : d0fe > bne * ;failed not equal (non zero) + > +1e62 : 28 > plp ;restore status + +1e63 : 88 dey +1e64 : cc1b02 cpy abs7f + tst_stat ~fn +1e67 : 08 > php ;save status +1e68 : 68 > pla ;use stack to retrieve status +1e69 : 48 > pha + > cmp_flag ~fn +1e6a : c97f > cmp #(~fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1e6c : d0fe > bne * ;failed not equal (non zero) + > +1e6e : 28 > plp ;restore status + +1e6f : 88 dey +1e70 : cc1b02 cpy abs7f + tst_y $7e,~fzc +1e73 : 08 > php ;save flags +1e74 : c07e > cpy #$7e ;test result + > trap_ne +1e76 : d0fe > bne * ;failed not equal (non zero) + > +1e78 : 68 > pla ;load status +1e79 : 48 > pha + > cmp_flag ~fzc +1e7a : c9fc > cmp #(~fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1e7c : d0fe > bne * ;failed not equal (non zero) + > +1e7e : 28 > plp ;restore status + + + set_y $80,0 + > load_flag 0 +1e7f : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1e81 : 48 > pha ;use stack to load status +1e82 : a080 > ldy #$80 ;precharge index y +1e84 : 28 > plp + +1e85 : c07f cpy #$7f + tst_stat fc +1e87 : 08 > php ;save status +1e88 : 68 > pla ;use stack to retrieve status +1e89 : 48 > pha + > cmp_flag fc +1e8a : c931 > cmp #(fc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1e8c : d0fe > bne * ;failed not equal (non zero) + > +1e8e : 28 > plp ;restore status + +1e8f : 88 dey +1e90 : c07f cpy #$7f + tst_stat fzc +1e92 : 08 > php ;save status +1e93 : 68 > pla ;use stack to retrieve status +1e94 : 48 > pha + > cmp_flag fzc +1e95 : c933 > cmp #(fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1e97 : d0fe > bne * ;failed not equal (non zero) + > +1e99 : 28 > plp ;restore status + +1e9a : 88 dey +1e9b : c07f cpy #$7f + tst_y $7e,fn +1e9d : 08 > php ;save flags +1e9e : c07e > cpy #$7e ;test result + > trap_ne +1ea0 : d0fe > bne * ;failed not equal (non zero) + > +1ea2 : 68 > pla ;load status +1ea3 : 48 > pha + > cmp_flag fn +1ea4 : c9b0 > cmp #(fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1ea6 : d0fe > bne * ;failed not equal (non zero) + > +1ea8 : 28 > plp ;restore status + + set_y $80,$ff + > load_flag $ff +1ea9 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1eab : 48 > pha ;use stack to load status +1eac : a080 > ldy #$80 ;precharge index y +1eae : 28 > plp + +1eaf : c07f cpy #$7f + tst_stat ~fnz +1eb1 : 08 > php ;save status +1eb2 : 68 > pla ;use stack to retrieve status +1eb3 : 48 > pha + > cmp_flag ~fnz +1eb4 : c97d > cmp #(~fnz|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1eb6 : d0fe > bne * ;failed not equal (non zero) + > +1eb8 : 28 > plp ;restore status + +1eb9 : 88 dey +1eba : c07f cpy #$7f + tst_stat ~fn +1ebc : 08 > php ;save status +1ebd : 68 > pla ;use stack to retrieve status +1ebe : 48 > pha + > cmp_flag ~fn +1ebf : c97f > cmp #(~fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1ec1 : d0fe > bne * ;failed not equal (non zero) + > +1ec3 : 28 > plp ;restore status + +1ec4 : 88 dey +1ec5 : c07f cpy #$7f + tst_y $7e,~fzc +1ec7 : 08 > php ;save flags +1ec8 : c07e > cpy #$7e ;test result + > trap_ne +1eca : d0fe > bne * ;failed not equal (non zero) + > +1ecc : 68 > pla ;load status +1ecd : 48 > pha + > cmp_flag ~fzc +1ece : c9fc > cmp #(~fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1ed0 : d0fe > bne * ;failed not equal (non zero) + > +1ed2 : 28 > plp ;restore status + + next_test +1ed3 : ad0002 > lda test_case ;previous test +1ed6 : c91b > cmp #test_num + > trap_ne ;test is out of sequence +1ed8 : d0fe > bne * ;failed not equal (non zero) + > +001c = >test_num = test_num + 1 +1eda : a91c > lda #test_num ;*** next tests' number +1edc : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; CMP - zp / abs / # + set_a $80,0 + > load_flag 0 +1edf : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1ee1 : 48 > pha ;use stack to load status +1ee2 : a980 > lda #$80 ;precharge accu +1ee4 : 28 > plp + +1ee5 : c517 cmp zp7f + tst_a $80,fc +1ee7 : 08 > php ;save flags +1ee8 : c980 > cmp #$80 ;test result + > trap_ne +1eea : d0fe > bne * ;failed not equal (non zero) + > +1eec : 68 > pla ;load status +1eed : 48 > pha + > cmp_flag fc +1eee : c931 > cmp #(fc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1ef0 : d0fe > bne * ;failed not equal (non zero) + > +1ef2 : 28 > plp ;restore status + + set_a $7f,0 + > load_flag 0 +1ef3 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1ef5 : 48 > pha ;use stack to load status +1ef6 : a97f > lda #$7f ;precharge accu +1ef8 : 28 > plp + +1ef9 : c517 cmp zp7f + tst_a $7f,fzc +1efb : 08 > php ;save flags +1efc : c97f > cmp #$7f ;test result + > trap_ne +1efe : d0fe > bne * ;failed not equal (non zero) + > +1f00 : 68 > pla ;load status +1f01 : 48 > pha + > cmp_flag fzc +1f02 : c933 > cmp #(fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1f04 : d0fe > bne * ;failed not equal (non zero) + > +1f06 : 28 > plp ;restore status + + set_a $7e,0 + > load_flag 0 +1f07 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1f09 : 48 > pha ;use stack to load status +1f0a : a97e > lda #$7e ;precharge accu +1f0c : 28 > plp + +1f0d : c517 cmp zp7f + tst_a $7e,fn +1f0f : 08 > php ;save flags +1f10 : c97e > cmp #$7e ;test result + > trap_ne +1f12 : d0fe > bne * ;failed not equal (non zero) + > +1f14 : 68 > pla ;load status +1f15 : 48 > pha + > cmp_flag fn +1f16 : c9b0 > cmp #(fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1f18 : d0fe > bne * ;failed not equal (non zero) + > +1f1a : 28 > plp ;restore status + + set_a $80,$ff + > load_flag $ff +1f1b : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1f1d : 48 > pha ;use stack to load status +1f1e : a980 > lda #$80 ;precharge accu +1f20 : 28 > plp + +1f21 : c517 cmp zp7f + tst_a $80,~fnz +1f23 : 08 > php ;save flags +1f24 : c980 > cmp #$80 ;test result + > trap_ne +1f26 : d0fe > bne * ;failed not equal (non zero) + > +1f28 : 68 > pla ;load status +1f29 : 48 > pha + > cmp_flag ~fnz +1f2a : c97d > cmp #(~fnz|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1f2c : d0fe > bne * ;failed not equal (non zero) + > +1f2e : 28 > plp ;restore status + + set_a $7f,$ff + > load_flag $ff +1f2f : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1f31 : 48 > pha ;use stack to load status +1f32 : a97f > lda #$7f ;precharge accu +1f34 : 28 > plp + +1f35 : c517 cmp zp7f + tst_a $7f,~fn +1f37 : 08 > php ;save flags +1f38 : c97f > cmp #$7f ;test result + > trap_ne +1f3a : d0fe > bne * ;failed not equal (non zero) + > +1f3c : 68 > pla ;load status +1f3d : 48 > pha + > cmp_flag ~fn +1f3e : c97f > cmp #(~fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1f40 : d0fe > bne * ;failed not equal (non zero) + > +1f42 : 28 > plp ;restore status + + set_a $7e,$ff + > load_flag $ff +1f43 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1f45 : 48 > pha ;use stack to load status +1f46 : a97e > lda #$7e ;precharge accu +1f48 : 28 > plp + +1f49 : c517 cmp zp7f + tst_a $7e,~fzc +1f4b : 08 > php ;save flags +1f4c : c97e > cmp #$7e ;test result + > trap_ne +1f4e : d0fe > bne * ;failed not equal (non zero) + > +1f50 : 68 > pla ;load status +1f51 : 48 > pha + > cmp_flag ~fzc +1f52 : c9fc > cmp #(~fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1f54 : d0fe > bne * ;failed not equal (non zero) + > +1f56 : 28 > plp ;restore status + + + set_a $80,0 + > load_flag 0 +1f57 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1f59 : 48 > pha ;use stack to load status +1f5a : a980 > lda #$80 ;precharge accu +1f5c : 28 > plp + +1f5d : cd1b02 cmp abs7f + tst_a $80,fc +1f60 : 08 > php ;save flags +1f61 : c980 > cmp #$80 ;test result + > trap_ne +1f63 : d0fe > bne * ;failed not equal (non zero) + > +1f65 : 68 > pla ;load status +1f66 : 48 > pha + > cmp_flag fc +1f67 : c931 > cmp #(fc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1f69 : d0fe > bne * ;failed not equal (non zero) + > +1f6b : 28 > plp ;restore status + + set_a $7f,0 + > load_flag 0 +1f6c : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1f6e : 48 > pha ;use stack to load status +1f6f : a97f > lda #$7f ;precharge accu +1f71 : 28 > plp + +1f72 : cd1b02 cmp abs7f + tst_a $7f,fzc +1f75 : 08 > php ;save flags +1f76 : c97f > cmp #$7f ;test result + > trap_ne +1f78 : d0fe > bne * ;failed not equal (non zero) + > +1f7a : 68 > pla ;load status +1f7b : 48 > pha + > cmp_flag fzc +1f7c : c933 > cmp #(fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1f7e : d0fe > bne * ;failed not equal (non zero) + > +1f80 : 28 > plp ;restore status + + set_a $7e,0 + > load_flag 0 +1f81 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1f83 : 48 > pha ;use stack to load status +1f84 : a97e > lda #$7e ;precharge accu +1f86 : 28 > plp + +1f87 : cd1b02 cmp abs7f + tst_a $7e,fn +1f8a : 08 > php ;save flags +1f8b : c97e > cmp #$7e ;test result + > trap_ne +1f8d : d0fe > bne * ;failed not equal (non zero) + > +1f8f : 68 > pla ;load status +1f90 : 48 > pha + > cmp_flag fn +1f91 : c9b0 > cmp #(fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1f93 : d0fe > bne * ;failed not equal (non zero) + > +1f95 : 28 > plp ;restore status + + set_a $80,$ff + > load_flag $ff +1f96 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1f98 : 48 > pha ;use stack to load status +1f99 : a980 > lda #$80 ;precharge accu +1f9b : 28 > plp + +1f9c : cd1b02 cmp abs7f + tst_a $80,~fnz +1f9f : 08 > php ;save flags +1fa0 : c980 > cmp #$80 ;test result + > trap_ne +1fa2 : d0fe > bne * ;failed not equal (non zero) + > +1fa4 : 68 > pla ;load status +1fa5 : 48 > pha + > cmp_flag ~fnz +1fa6 : c97d > cmp #(~fnz|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1fa8 : d0fe > bne * ;failed not equal (non zero) + > +1faa : 28 > plp ;restore status + + set_a $7f,$ff + > load_flag $ff +1fab : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1fad : 48 > pha ;use stack to load status +1fae : a97f > lda #$7f ;precharge accu +1fb0 : 28 > plp + +1fb1 : cd1b02 cmp abs7f + tst_a $7f,~fn +1fb4 : 08 > php ;save flags +1fb5 : c97f > cmp #$7f ;test result + > trap_ne +1fb7 : d0fe > bne * ;failed not equal (non zero) + > +1fb9 : 68 > pla ;load status +1fba : 48 > pha + > cmp_flag ~fn +1fbb : c97f > cmp #(~fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1fbd : d0fe > bne * ;failed not equal (non zero) + > +1fbf : 28 > plp ;restore status + + set_a $7e,$ff + > load_flag $ff +1fc0 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +1fc2 : 48 > pha ;use stack to load status +1fc3 : a97e > lda #$7e ;precharge accu +1fc5 : 28 > plp + +1fc6 : cd1b02 cmp abs7f + tst_a $7e,~fzc +1fc9 : 08 > php ;save flags +1fca : c97e > cmp #$7e ;test result + > trap_ne +1fcc : d0fe > bne * ;failed not equal (non zero) + > +1fce : 68 > pla ;load status +1fcf : 48 > pha + > cmp_flag ~fzc +1fd0 : c9fc > cmp #(~fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1fd2 : d0fe > bne * ;failed not equal (non zero) + > +1fd4 : 28 > plp ;restore status + + + set_a $80,0 + > load_flag 0 +1fd5 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1fd7 : 48 > pha ;use stack to load status +1fd8 : a980 > lda #$80 ;precharge accu +1fda : 28 > plp + +1fdb : c97f cmp #$7f + tst_a $80,fc +1fdd : 08 > php ;save flags +1fde : c980 > cmp #$80 ;test result + > trap_ne +1fe0 : d0fe > bne * ;failed not equal (non zero) + > +1fe2 : 68 > pla ;load status +1fe3 : 48 > pha + > cmp_flag fc +1fe4 : c931 > cmp #(fc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1fe6 : d0fe > bne * ;failed not equal (non zero) + > +1fe8 : 28 > plp ;restore status + + set_a $7f,0 + > load_flag 0 +1fe9 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1feb : 48 > pha ;use stack to load status +1fec : a97f > lda #$7f ;precharge accu +1fee : 28 > plp + +1fef : c97f cmp #$7f + tst_a $7f,fzc +1ff1 : 08 > php ;save flags +1ff2 : c97f > cmp #$7f ;test result + > trap_ne +1ff4 : d0fe > bne * ;failed not equal (non zero) + > +1ff6 : 68 > pla ;load status +1ff7 : 48 > pha + > cmp_flag fzc +1ff8 : c933 > cmp #(fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +1ffa : d0fe > bne * ;failed not equal (non zero) + > +1ffc : 28 > plp ;restore status + + set_a $7e,0 + > load_flag 0 +1ffd : a900 > lda #0 ;allow test to change I-flag (no mask) + > +1fff : 48 > pha ;use stack to load status +2000 : a97e > lda #$7e ;precharge accu +2002 : 28 > plp + +2003 : c97f cmp #$7f + tst_a $7e,fn +2005 : 08 > php ;save flags +2006 : c97e > cmp #$7e ;test result + > trap_ne +2008 : d0fe > bne * ;failed not equal (non zero) + > +200a : 68 > pla ;load status +200b : 48 > pha + > cmp_flag fn +200c : c9b0 > cmp #(fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +200e : d0fe > bne * ;failed not equal (non zero) + > +2010 : 28 > plp ;restore status + + set_a $80,$ff + > load_flag $ff +2011 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2013 : 48 > pha ;use stack to load status +2014 : a980 > lda #$80 ;precharge accu +2016 : 28 > plp + +2017 : c97f cmp #$7f + tst_a $80,~fnz +2019 : 08 > php ;save flags +201a : c980 > cmp #$80 ;test result + > trap_ne +201c : d0fe > bne * ;failed not equal (non zero) + > +201e : 68 > pla ;load status +201f : 48 > pha + > cmp_flag ~fnz +2020 : c97d > cmp #(~fnz|fao)&m8 ;expected flags + always on bits + > + > trap_ne +2022 : d0fe > bne * ;failed not equal (non zero) + > +2024 : 28 > plp ;restore status + + set_a $7f,$ff + > load_flag $ff +2025 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2027 : 48 > pha ;use stack to load status +2028 : a97f > lda #$7f ;precharge accu +202a : 28 > plp + +202b : c97f cmp #$7f + tst_a $7f,~fn +202d : 08 > php ;save flags +202e : c97f > cmp #$7f ;test result + > trap_ne +2030 : d0fe > bne * ;failed not equal (non zero) + > +2032 : 68 > pla ;load status +2033 : 48 > pha + > cmp_flag ~fn +2034 : c97f > cmp #(~fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +2036 : d0fe > bne * ;failed not equal (non zero) + > +2038 : 28 > plp ;restore status + + set_a $7e,$ff + > load_flag $ff +2039 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +203b : 48 > pha ;use stack to load status +203c : a97e > lda #$7e ;precharge accu +203e : 28 > plp + +203f : c97f cmp #$7f + tst_a $7e,~fzc +2041 : 08 > php ;save flags +2042 : c97e > cmp #$7e ;test result + > trap_ne +2044 : d0fe > bne * ;failed not equal (non zero) + > +2046 : 68 > pla ;load status +2047 : 48 > pha + > cmp_flag ~fzc +2048 : c9fc > cmp #(~fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +204a : d0fe > bne * ;failed not equal (non zero) + > +204c : 28 > plp ;restore status + + +204d : a204 ldx #4 ;with indexing by X + set_a $80,0 + > load_flag 0 +204f : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2051 : 48 > pha ;use stack to load status +2052 : a980 > lda #$80 ;precharge accu +2054 : 28 > plp + +2055 : d513 cmp zp1,x + tst_a $80,fc +2057 : 08 > php ;save flags +2058 : c980 > cmp #$80 ;test result + > trap_ne +205a : d0fe > bne * ;failed not equal (non zero) + > +205c : 68 > pla ;load status +205d : 48 > pha + > cmp_flag fc +205e : c931 > cmp #(fc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +2060 : d0fe > bne * ;failed not equal (non zero) + > +2062 : 28 > plp ;restore status + + set_a $7f,0 + > load_flag 0 +2063 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2065 : 48 > pha ;use stack to load status +2066 : a97f > lda #$7f ;precharge accu +2068 : 28 > plp + +2069 : d513 cmp zp1,x + tst_a $7f,fzc +206b : 08 > php ;save flags +206c : c97f > cmp #$7f ;test result + > trap_ne +206e : d0fe > bne * ;failed not equal (non zero) + > +2070 : 68 > pla ;load status +2071 : 48 > pha + > cmp_flag fzc +2072 : c933 > cmp #(fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +2074 : d0fe > bne * ;failed not equal (non zero) + > +2076 : 28 > plp ;restore status + + set_a $7e,0 + > load_flag 0 +2077 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2079 : 48 > pha ;use stack to load status +207a : a97e > lda #$7e ;precharge accu +207c : 28 > plp + +207d : d513 cmp zp1,x + tst_a $7e,fn +207f : 08 > php ;save flags +2080 : c97e > cmp #$7e ;test result + > trap_ne +2082 : d0fe > bne * ;failed not equal (non zero) + > +2084 : 68 > pla ;load status +2085 : 48 > pha + > cmp_flag fn +2086 : c9b0 > cmp #(fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +2088 : d0fe > bne * ;failed not equal (non zero) + > +208a : 28 > plp ;restore status + + set_a $80,$ff + > load_flag $ff +208b : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +208d : 48 > pha ;use stack to load status +208e : a980 > lda #$80 ;precharge accu +2090 : 28 > plp + +2091 : d513 cmp zp1,x + tst_a $80,~fnz +2093 : 08 > php ;save flags +2094 : c980 > cmp #$80 ;test result + > trap_ne +2096 : d0fe > bne * ;failed not equal (non zero) + > +2098 : 68 > pla ;load status +2099 : 48 > pha + > cmp_flag ~fnz +209a : c97d > cmp #(~fnz|fao)&m8 ;expected flags + always on bits + > + > trap_ne +209c : d0fe > bne * ;failed not equal (non zero) + > +209e : 28 > plp ;restore status + + set_a $7f,$ff + > load_flag $ff +209f : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +20a1 : 48 > pha ;use stack to load status +20a2 : a97f > lda #$7f ;precharge accu +20a4 : 28 > plp + +20a5 : d513 cmp zp1,x + tst_a $7f,~fn +20a7 : 08 > php ;save flags +20a8 : c97f > cmp #$7f ;test result + > trap_ne +20aa : d0fe > bne * ;failed not equal (non zero) + > +20ac : 68 > pla ;load status +20ad : 48 > pha + > cmp_flag ~fn +20ae : c97f > cmp #(~fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +20b0 : d0fe > bne * ;failed not equal (non zero) + > +20b2 : 28 > plp ;restore status + + set_a $7e,$ff + > load_flag $ff +20b3 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +20b5 : 48 > pha ;use stack to load status +20b6 : a97e > lda #$7e ;precharge accu +20b8 : 28 > plp + +20b9 : d513 cmp zp1,x + tst_a $7e,~fzc +20bb : 08 > php ;save flags +20bc : c97e > cmp #$7e ;test result + > trap_ne +20be : d0fe > bne * ;failed not equal (non zero) + > +20c0 : 68 > pla ;load status +20c1 : 48 > pha + > cmp_flag ~fzc +20c2 : c9fc > cmp #(~fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +20c4 : d0fe > bne * ;failed not equal (non zero) + > +20c6 : 28 > plp ;restore status + + + set_a $80,0 + > load_flag 0 +20c7 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +20c9 : 48 > pha ;use stack to load status +20ca : a980 > lda #$80 ;precharge accu +20cc : 28 > plp + +20cd : dd1702 cmp abs1,x + tst_a $80,fc +20d0 : 08 > php ;save flags +20d1 : c980 > cmp #$80 ;test result + > trap_ne +20d3 : d0fe > bne * ;failed not equal (non zero) + > +20d5 : 68 > pla ;load status +20d6 : 48 > pha + > cmp_flag fc +20d7 : c931 > cmp #(fc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +20d9 : d0fe > bne * ;failed not equal (non zero) + > +20db : 28 > plp ;restore status + + set_a $7f,0 + > load_flag 0 +20dc : a900 > lda #0 ;allow test to change I-flag (no mask) + > +20de : 48 > pha ;use stack to load status +20df : a97f > lda #$7f ;precharge accu +20e1 : 28 > plp + +20e2 : dd1702 cmp abs1,x + tst_a $7f,fzc +20e5 : 08 > php ;save flags +20e6 : c97f > cmp #$7f ;test result + > trap_ne +20e8 : d0fe > bne * ;failed not equal (non zero) + > +20ea : 68 > pla ;load status +20eb : 48 > pha + > cmp_flag fzc +20ec : c933 > cmp #(fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +20ee : d0fe > bne * ;failed not equal (non zero) + > +20f0 : 28 > plp ;restore status + + set_a $7e,0 + > load_flag 0 +20f1 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +20f3 : 48 > pha ;use stack to load status +20f4 : a97e > lda #$7e ;precharge accu +20f6 : 28 > plp + +20f7 : dd1702 cmp abs1,x + tst_a $7e,fn +20fa : 08 > php ;save flags +20fb : c97e > cmp #$7e ;test result + > trap_ne +20fd : d0fe > bne * ;failed not equal (non zero) + > +20ff : 68 > pla ;load status +2100 : 48 > pha + > cmp_flag fn +2101 : c9b0 > cmp #(fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +2103 : d0fe > bne * ;failed not equal (non zero) + > +2105 : 28 > plp ;restore status + + set_a $80,$ff + > load_flag $ff +2106 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2108 : 48 > pha ;use stack to load status +2109 : a980 > lda #$80 ;precharge accu +210b : 28 > plp + +210c : dd1702 cmp abs1,x + tst_a $80,~fnz +210f : 08 > php ;save flags +2110 : c980 > cmp #$80 ;test result + > trap_ne +2112 : d0fe > bne * ;failed not equal (non zero) + > +2114 : 68 > pla ;load status +2115 : 48 > pha + > cmp_flag ~fnz +2116 : c97d > cmp #(~fnz|fao)&m8 ;expected flags + always on bits + > + > trap_ne +2118 : d0fe > bne * ;failed not equal (non zero) + > +211a : 28 > plp ;restore status + + set_a $7f,$ff + > load_flag $ff +211b : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +211d : 48 > pha ;use stack to load status +211e : a97f > lda #$7f ;precharge accu +2120 : 28 > plp + +2121 : dd1702 cmp abs1,x + tst_a $7f,~fn +2124 : 08 > php ;save flags +2125 : c97f > cmp #$7f ;test result + > trap_ne +2127 : d0fe > bne * ;failed not equal (non zero) + > +2129 : 68 > pla ;load status +212a : 48 > pha + > cmp_flag ~fn +212b : c97f > cmp #(~fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +212d : d0fe > bne * ;failed not equal (non zero) + > +212f : 28 > plp ;restore status + + set_a $7e,$ff + > load_flag $ff +2130 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2132 : 48 > pha ;use stack to load status +2133 : a97e > lda #$7e ;precharge accu +2135 : 28 > plp + +2136 : dd1702 cmp abs1,x + tst_a $7e,~fzc +2139 : 08 > php ;save flags +213a : c97e > cmp #$7e ;test result + > trap_ne +213c : d0fe > bne * ;failed not equal (non zero) + > +213e : 68 > pla ;load status +213f : 48 > pha + > cmp_flag ~fzc +2140 : c9fc > cmp #(~fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +2142 : d0fe > bne * ;failed not equal (non zero) + > +2144 : 28 > plp ;restore status + + +2145 : a004 ldy #4 ;with indexing by Y +2147 : a208 ldx #8 ;with indexed indirect + set_a $80,0 + > load_flag 0 +2149 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +214b : 48 > pha ;use stack to load status +214c : a980 > lda #$80 ;precharge accu +214e : 28 > plp + +214f : d91702 cmp abs1,y + tst_a $80,fc +2152 : 08 > php ;save flags +2153 : c980 > cmp #$80 ;test result + > trap_ne +2155 : d0fe > bne * ;failed not equal (non zero) + > +2157 : 68 > pla ;load status +2158 : 48 > pha + > cmp_flag fc +2159 : c931 > cmp #(fc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +215b : d0fe > bne * ;failed not equal (non zero) + > +215d : 28 > plp ;restore status + + set_a $7f,0 + > load_flag 0 +215e : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2160 : 48 > pha ;use stack to load status +2161 : a97f > lda #$7f ;precharge accu +2163 : 28 > plp + +2164 : d91702 cmp abs1,y + tst_a $7f,fzc +2167 : 08 > php ;save flags +2168 : c97f > cmp #$7f ;test result + > trap_ne +216a : d0fe > bne * ;failed not equal (non zero) + > +216c : 68 > pla ;load status +216d : 48 > pha + > cmp_flag fzc +216e : c933 > cmp #(fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +2170 : d0fe > bne * ;failed not equal (non zero) + > +2172 : 28 > plp ;restore status + + set_a $7e,0 + > load_flag 0 +2173 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2175 : 48 > pha ;use stack to load status +2176 : a97e > lda #$7e ;precharge accu +2178 : 28 > plp + +2179 : d91702 cmp abs1,y + tst_a $7e,fn +217c : 08 > php ;save flags +217d : c97e > cmp #$7e ;test result + > trap_ne +217f : d0fe > bne * ;failed not equal (non zero) + > +2181 : 68 > pla ;load status +2182 : 48 > pha + > cmp_flag fn +2183 : c9b0 > cmp #(fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +2185 : d0fe > bne * ;failed not equal (non zero) + > +2187 : 28 > plp ;restore status + + set_a $80,$ff + > load_flag $ff +2188 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +218a : 48 > pha ;use stack to load status +218b : a980 > lda #$80 ;precharge accu +218d : 28 > plp + +218e : d91702 cmp abs1,y + tst_a $80,~fnz +2191 : 08 > php ;save flags +2192 : c980 > cmp #$80 ;test result + > trap_ne +2194 : d0fe > bne * ;failed not equal (non zero) + > +2196 : 68 > pla ;load status +2197 : 48 > pha + > cmp_flag ~fnz +2198 : c97d > cmp #(~fnz|fao)&m8 ;expected flags + always on bits + > + > trap_ne +219a : d0fe > bne * ;failed not equal (non zero) + > +219c : 28 > plp ;restore status + + set_a $7f,$ff + > load_flag $ff +219d : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +219f : 48 > pha ;use stack to load status +21a0 : a97f > lda #$7f ;precharge accu +21a2 : 28 > plp + +21a3 : d91702 cmp abs1,y + tst_a $7f,~fn +21a6 : 08 > php ;save flags +21a7 : c97f > cmp #$7f ;test result + > trap_ne +21a9 : d0fe > bne * ;failed not equal (non zero) + > +21ab : 68 > pla ;load status +21ac : 48 > pha + > cmp_flag ~fn +21ad : c97f > cmp #(~fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +21af : d0fe > bne * ;failed not equal (non zero) + > +21b1 : 28 > plp ;restore status + + set_a $7e,$ff + > load_flag $ff +21b2 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +21b4 : 48 > pha ;use stack to load status +21b5 : a97e > lda #$7e ;precharge accu +21b7 : 28 > plp + +21b8 : d91702 cmp abs1,y + tst_a $7e,~fzc +21bb : 08 > php ;save flags +21bc : c97e > cmp #$7e ;test result + > trap_ne +21be : d0fe > bne * ;failed not equal (non zero) + > +21c0 : 68 > pla ;load status +21c1 : 48 > pha + > cmp_flag ~fzc +21c2 : c9fc > cmp #(~fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +21c4 : d0fe > bne * ;failed not equal (non zero) + > +21c6 : 28 > plp ;restore status + + + set_a $80,0 + > load_flag 0 +21c7 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +21c9 : 48 > pha ;use stack to load status +21ca : a980 > lda #$80 ;precharge accu +21cc : 28 > plp + +21cd : c124 cmp (ind1,x) + tst_a $80,fc +21cf : 08 > php ;save flags +21d0 : c980 > cmp #$80 ;test result + > trap_ne +21d2 : d0fe > bne * ;failed not equal (non zero) + > +21d4 : 68 > pla ;load status +21d5 : 48 > pha + > cmp_flag fc +21d6 : c931 > cmp #(fc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +21d8 : d0fe > bne * ;failed not equal (non zero) + > +21da : 28 > plp ;restore status + + set_a $7f,0 + > load_flag 0 +21db : a900 > lda #0 ;allow test to change I-flag (no mask) + > +21dd : 48 > pha ;use stack to load status +21de : a97f > lda #$7f ;precharge accu +21e0 : 28 > plp + +21e1 : c124 cmp (ind1,x) + tst_a $7f,fzc +21e3 : 08 > php ;save flags +21e4 : c97f > cmp #$7f ;test result + > trap_ne +21e6 : d0fe > bne * ;failed not equal (non zero) + > +21e8 : 68 > pla ;load status +21e9 : 48 > pha + > cmp_flag fzc +21ea : c933 > cmp #(fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +21ec : d0fe > bne * ;failed not equal (non zero) + > +21ee : 28 > plp ;restore status + + set_a $7e,0 + > load_flag 0 +21ef : a900 > lda #0 ;allow test to change I-flag (no mask) + > +21f1 : 48 > pha ;use stack to load status +21f2 : a97e > lda #$7e ;precharge accu +21f4 : 28 > plp + +21f5 : c124 cmp (ind1,x) + tst_a $7e,fn +21f7 : 08 > php ;save flags +21f8 : c97e > cmp #$7e ;test result + > trap_ne +21fa : d0fe > bne * ;failed not equal (non zero) + > +21fc : 68 > pla ;load status +21fd : 48 > pha + > cmp_flag fn +21fe : c9b0 > cmp #(fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +2200 : d0fe > bne * ;failed not equal (non zero) + > +2202 : 28 > plp ;restore status + + set_a $80,$ff + > load_flag $ff +2203 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2205 : 48 > pha ;use stack to load status +2206 : a980 > lda #$80 ;precharge accu +2208 : 28 > plp + +2209 : c124 cmp (ind1,x) + tst_a $80,~fnz +220b : 08 > php ;save flags +220c : c980 > cmp #$80 ;test result + > trap_ne +220e : d0fe > bne * ;failed not equal (non zero) + > +2210 : 68 > pla ;load status +2211 : 48 > pha + > cmp_flag ~fnz +2212 : c97d > cmp #(~fnz|fao)&m8 ;expected flags + always on bits + > + > trap_ne +2214 : d0fe > bne * ;failed not equal (non zero) + > +2216 : 28 > plp ;restore status + + set_a $7f,$ff + > load_flag $ff +2217 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2219 : 48 > pha ;use stack to load status +221a : a97f > lda #$7f ;precharge accu +221c : 28 > plp + +221d : c124 cmp (ind1,x) + tst_a $7f,~fn +221f : 08 > php ;save flags +2220 : c97f > cmp #$7f ;test result + > trap_ne +2222 : d0fe > bne * ;failed not equal (non zero) + > +2224 : 68 > pla ;load status +2225 : 48 > pha + > cmp_flag ~fn +2226 : c97f > cmp #(~fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +2228 : d0fe > bne * ;failed not equal (non zero) + > +222a : 28 > plp ;restore status + + set_a $7e,$ff + > load_flag $ff +222b : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +222d : 48 > pha ;use stack to load status +222e : a97e > lda #$7e ;precharge accu +2230 : 28 > plp + +2231 : c124 cmp (ind1,x) + tst_a $7e,~fzc +2233 : 08 > php ;save flags +2234 : c97e > cmp #$7e ;test result + > trap_ne +2236 : d0fe > bne * ;failed not equal (non zero) + > +2238 : 68 > pla ;load status +2239 : 48 > pha + > cmp_flag ~fzc +223a : c9fc > cmp #(~fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +223c : d0fe > bne * ;failed not equal (non zero) + > +223e : 28 > plp ;restore status + + + set_a $80,0 + > load_flag 0 +223f : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2241 : 48 > pha ;use stack to load status +2242 : a980 > lda #$80 ;precharge accu +2244 : 28 > plp + +2245 : d124 cmp (ind1),y + tst_a $80,fc +2247 : 08 > php ;save flags +2248 : c980 > cmp #$80 ;test result + > trap_ne +224a : d0fe > bne * ;failed not equal (non zero) + > +224c : 68 > pla ;load status +224d : 48 > pha + > cmp_flag fc +224e : c931 > cmp #(fc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +2250 : d0fe > bne * ;failed not equal (non zero) + > +2252 : 28 > plp ;restore status + + set_a $7f,0 + > load_flag 0 +2253 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2255 : 48 > pha ;use stack to load status +2256 : a97f > lda #$7f ;precharge accu +2258 : 28 > plp + +2259 : d124 cmp (ind1),y + tst_a $7f,fzc +225b : 08 > php ;save flags +225c : c97f > cmp #$7f ;test result + > trap_ne +225e : d0fe > bne * ;failed not equal (non zero) + > +2260 : 68 > pla ;load status +2261 : 48 > pha + > cmp_flag fzc +2262 : c933 > cmp #(fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +2264 : d0fe > bne * ;failed not equal (non zero) + > +2266 : 28 > plp ;restore status + + set_a $7e,0 + > load_flag 0 +2267 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2269 : 48 > pha ;use stack to load status +226a : a97e > lda #$7e ;precharge accu +226c : 28 > plp + +226d : d124 cmp (ind1),y + tst_a $7e,fn +226f : 08 > php ;save flags +2270 : c97e > cmp #$7e ;test result + > trap_ne +2272 : d0fe > bne * ;failed not equal (non zero) + > +2274 : 68 > pla ;load status +2275 : 48 > pha + > cmp_flag fn +2276 : c9b0 > cmp #(fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +2278 : d0fe > bne * ;failed not equal (non zero) + > +227a : 28 > plp ;restore status + + set_a $80,$ff + > load_flag $ff +227b : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +227d : 48 > pha ;use stack to load status +227e : a980 > lda #$80 ;precharge accu +2280 : 28 > plp + +2281 : d124 cmp (ind1),y + tst_a $80,~fnz +2283 : 08 > php ;save flags +2284 : c980 > cmp #$80 ;test result + > trap_ne +2286 : d0fe > bne * ;failed not equal (non zero) + > +2288 : 68 > pla ;load status +2289 : 48 > pha + > cmp_flag ~fnz +228a : c97d > cmp #(~fnz|fao)&m8 ;expected flags + always on bits + > + > trap_ne +228c : d0fe > bne * ;failed not equal (non zero) + > +228e : 28 > plp ;restore status + + set_a $7f,$ff + > load_flag $ff +228f : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2291 : 48 > pha ;use stack to load status +2292 : a97f > lda #$7f ;precharge accu +2294 : 28 > plp + +2295 : d124 cmp (ind1),y + tst_a $7f,~fn +2297 : 08 > php ;save flags +2298 : c97f > cmp #$7f ;test result + > trap_ne +229a : d0fe > bne * ;failed not equal (non zero) + > +229c : 68 > pla ;load status +229d : 48 > pha + > cmp_flag ~fn +229e : c97f > cmp #(~fn|fao)&m8 ;expected flags + always on bits + > + > trap_ne +22a0 : d0fe > bne * ;failed not equal (non zero) + > +22a2 : 28 > plp ;restore status + + set_a $7e,$ff + > load_flag $ff +22a3 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +22a5 : 48 > pha ;use stack to load status +22a6 : a97e > lda #$7e ;precharge accu +22a8 : 28 > plp + +22a9 : d124 cmp (ind1),y + tst_a $7e,~fzc +22ab : 08 > php ;save flags +22ac : c97e > cmp #$7e ;test result + > trap_ne +22ae : d0fe > bne * ;failed not equal (non zero) + > +22b0 : 68 > pla ;load status +22b1 : 48 > pha + > cmp_flag ~fzc +22b2 : c9fc > cmp #(~fzc|fao)&m8 ;expected flags + always on bits + > + > trap_ne +22b4 : d0fe > bne * ;failed not equal (non zero) + > +22b6 : 28 > plp ;restore status + + next_test +22b7 : ad0002 > lda test_case ;previous test +22ba : c91c > cmp #test_num + > trap_ne ;test is out of sequence +22bc : d0fe > bne * ;failed not equal (non zero) + > +001d = >test_num = test_num + 1 +22be : a91d > lda #test_num ;*** next tests' number +22c0 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; testing shifts - ASL LSR ROL ROR all addressing modes + ; shifts - accumulator +22c3 : a203 ldx #3 +22c5 : tasl + set_ax zp1,0 + > load_flag 0 +22c5 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +22c7 : 48 > pha ;use stack to load status +22c8 : b513 > lda zp1,x ;precharge accu +22ca : 28 > plp + +22cb : 0a asl a + tst_ax rASL,fASL,0 +22cc : 08 > php ;save flags +22cd : dd2002 > cmp rASL,x ;test result + > trap_ne +22d0 : d0fe > bne * ;failed not equal (non zero) + > +22d2 : 68 > pla ;load status + > eor_flag 0 +22d3 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +22d5 : dd3002 > cmp fASL,x ;test flags + > trap_ne ; +22d8 : d0fe > bne * ;failed not equal (non zero) + > + +22da : ca dex +22db : 10e8 bpl tasl +22dd : a203 ldx #3 +22df : tasl1 + set_ax zp1,$ff + > load_flag $ff +22df : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +22e1 : 48 > pha ;use stack to load status +22e2 : b513 > lda zp1,x ;precharge accu +22e4 : 28 > plp + +22e5 : 0a asl a + tst_ax rASL,fASL,$ff-fnzc +22e6 : 08 > php ;save flags +22e7 : dd2002 > cmp rASL,x ;test result + > trap_ne +22ea : d0fe > bne * ;failed not equal (non zero) + > +22ec : 68 > pla ;load status + > eor_flag $ff-fnzc +22ed : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +22ef : dd3002 > cmp fASL,x ;test flags + > trap_ne ; +22f2 : d0fe > bne * ;failed not equal (non zero) + > + +22f4 : ca dex +22f5 : 10e8 bpl tasl1 + +22f7 : a203 ldx #3 +22f9 : tlsr + set_ax zp1,0 + > load_flag 0 +22f9 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +22fb : 48 > pha ;use stack to load status +22fc : b513 > lda zp1,x ;precharge accu +22fe : 28 > plp + +22ff : 4a lsr a + tst_ax rLSR,fLSR,0 +2300 : 08 > php ;save flags +2301 : dd2802 > cmp rLSR,x ;test result + > trap_ne +2304 : d0fe > bne * ;failed not equal (non zero) + > +2306 : 68 > pla ;load status + > eor_flag 0 +2307 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2309 : dd3802 > cmp fLSR,x ;test flags + > trap_ne ; +230c : d0fe > bne * ;failed not equal (non zero) + > + +230e : ca dex +230f : 10e8 bpl tlsr +2311 : a203 ldx #3 +2313 : tlsr1 + set_ax zp1,$ff + > load_flag $ff +2313 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2315 : 48 > pha ;use stack to load status +2316 : b513 > lda zp1,x ;precharge accu +2318 : 28 > plp + +2319 : 4a lsr a + tst_ax rLSR,fLSR,$ff-fnzc +231a : 08 > php ;save flags +231b : dd2802 > cmp rLSR,x ;test result + > trap_ne +231e : d0fe > bne * ;failed not equal (non zero) + > +2320 : 68 > pla ;load status + > eor_flag $ff-fnzc +2321 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +2323 : dd3802 > cmp fLSR,x ;test flags + > trap_ne ; +2326 : d0fe > bne * ;failed not equal (non zero) + > + +2328 : ca dex +2329 : 10e8 bpl tlsr1 + +232b : a203 ldx #3 +232d : trol + set_ax zp1,0 + > load_flag 0 +232d : a900 > lda #0 ;allow test to change I-flag (no mask) + > +232f : 48 > pha ;use stack to load status +2330 : b513 > lda zp1,x ;precharge accu +2332 : 28 > plp + +2333 : 2a rol a + tst_ax rROL,fROL,0 +2334 : 08 > php ;save flags +2335 : dd2002 > cmp rROL,x ;test result + > trap_ne +2338 : d0fe > bne * ;failed not equal (non zero) + > +233a : 68 > pla ;load status + > eor_flag 0 +233b : 4930 > eor #0|fao ;invert expected flags + always on bits + > +233d : dd3002 > cmp fROL,x ;test flags + > trap_ne ; +2340 : d0fe > bne * ;failed not equal (non zero) + > + +2342 : ca dex +2343 : 10e8 bpl trol +2345 : a203 ldx #3 +2347 : trol1 + set_ax zp1,$ff-fc + > load_flag $ff-fc +2347 : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) + > +2349 : 48 > pha ;use stack to load status +234a : b513 > lda zp1,x ;precharge accu +234c : 28 > plp + +234d : 2a rol a + tst_ax rROL,fROL,$ff-fnzc +234e : 08 > php ;save flags +234f : dd2002 > cmp rROL,x ;test result + > trap_ne +2352 : d0fe > bne * ;failed not equal (non zero) + > +2354 : 68 > pla ;load status + > eor_flag $ff-fnzc +2355 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +2357 : dd3002 > cmp fROL,x ;test flags + > trap_ne ; +235a : d0fe > bne * ;failed not equal (non zero) + > + +235c : ca dex +235d : 10e8 bpl trol1 + +235f : a203 ldx #3 +2361 : trolc + set_ax zp1,fc + > load_flag fc +2361 : a901 > lda #fc ;allow test to change I-flag (no mask) + > +2363 : 48 > pha ;use stack to load status +2364 : b513 > lda zp1,x ;precharge accu +2366 : 28 > plp + +2367 : 2a rol a + tst_ax rROLc,fROLc,0 +2368 : 08 > php ;save flags +2369 : dd2402 > cmp rROLc,x ;test result + > trap_ne +236c : d0fe > bne * ;failed not equal (non zero) + > +236e : 68 > pla ;load status + > eor_flag 0 +236f : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2371 : dd3402 > cmp fROLc,x ;test flags + > trap_ne ; +2374 : d0fe > bne * ;failed not equal (non zero) + > + +2376 : ca dex +2377 : 10e8 bpl trolc +2379 : a203 ldx #3 +237b : trolc1 + set_ax zp1,$ff + > load_flag $ff +237b : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +237d : 48 > pha ;use stack to load status +237e : b513 > lda zp1,x ;precharge accu +2380 : 28 > plp + +2381 : 2a rol a + tst_ax rROLc,fROLc,$ff-fnzc +2382 : 08 > php ;save flags +2383 : dd2402 > cmp rROLc,x ;test result + > trap_ne +2386 : d0fe > bne * ;failed not equal (non zero) + > +2388 : 68 > pla ;load status + > eor_flag $ff-fnzc +2389 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +238b : dd3402 > cmp fROLc,x ;test flags + > trap_ne ; +238e : d0fe > bne * ;failed not equal (non zero) + > + +2390 : ca dex +2391 : 10e8 bpl trolc1 + +2393 : a203 ldx #3 +2395 : tror + set_ax zp1,0 + > load_flag 0 +2395 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2397 : 48 > pha ;use stack to load status +2398 : b513 > lda zp1,x ;precharge accu +239a : 28 > plp + +239b : 6a ror a + tst_ax rROR,fROR,0 +239c : 08 > php ;save flags +239d : dd2802 > cmp rROR,x ;test result + > trap_ne +23a0 : d0fe > bne * ;failed not equal (non zero) + > +23a2 : 68 > pla ;load status + > eor_flag 0 +23a3 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +23a5 : dd3802 > cmp fROR,x ;test flags + > trap_ne ; +23a8 : d0fe > bne * ;failed not equal (non zero) + > + +23aa : ca dex +23ab : 10e8 bpl tror +23ad : a203 ldx #3 +23af : tror1 + set_ax zp1,$ff-fc + > load_flag $ff-fc +23af : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) + > +23b1 : 48 > pha ;use stack to load status +23b2 : b513 > lda zp1,x ;precharge accu +23b4 : 28 > plp + +23b5 : 6a ror a + tst_ax rROR,fROR,$ff-fnzc +23b6 : 08 > php ;save flags +23b7 : dd2802 > cmp rROR,x ;test result + > trap_ne +23ba : d0fe > bne * ;failed not equal (non zero) + > +23bc : 68 > pla ;load status + > eor_flag $ff-fnzc +23bd : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +23bf : dd3802 > cmp fROR,x ;test flags + > trap_ne ; +23c2 : d0fe > bne * ;failed not equal (non zero) + > + +23c4 : ca dex +23c5 : 10e8 bpl tror1 + +23c7 : a203 ldx #3 +23c9 : trorc + set_ax zp1,fc + > load_flag fc +23c9 : a901 > lda #fc ;allow test to change I-flag (no mask) + > +23cb : 48 > pha ;use stack to load status +23cc : b513 > lda zp1,x ;precharge accu +23ce : 28 > plp + +23cf : 6a ror a + tst_ax rRORc,fRORc,0 +23d0 : 08 > php ;save flags +23d1 : dd2c02 > cmp rRORc,x ;test result + > trap_ne +23d4 : d0fe > bne * ;failed not equal (non zero) + > +23d6 : 68 > pla ;load status + > eor_flag 0 +23d7 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +23d9 : dd3c02 > cmp fRORc,x ;test flags + > trap_ne ; +23dc : d0fe > bne * ;failed not equal (non zero) + > + +23de : ca dex +23df : 10e8 bpl trorc +23e1 : a203 ldx #3 +23e3 : trorc1 + set_ax zp1,$ff + > load_flag $ff +23e3 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +23e5 : 48 > pha ;use stack to load status +23e6 : b513 > lda zp1,x ;precharge accu +23e8 : 28 > plp + +23e9 : 6a ror a + tst_ax rRORc,fRORc,$ff-fnzc +23ea : 08 > php ;save flags +23eb : dd2c02 > cmp rRORc,x ;test result + > trap_ne +23ee : d0fe > bne * ;failed not equal (non zero) + > +23f0 : 68 > pla ;load status + > eor_flag $ff-fnzc +23f1 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +23f3 : dd3c02 > cmp fRORc,x ;test flags + > trap_ne ; +23f6 : d0fe > bne * ;failed not equal (non zero) + > + +23f8 : ca dex +23f9 : 10e8 bpl trorc1 + next_test +23fb : ad0002 > lda test_case ;previous test +23fe : c91d > cmp #test_num + > trap_ne ;test is out of sequence +2400 : d0fe > bne * ;failed not equal (non zero) + > +001e = >test_num = test_num + 1 +2402 : a91e > lda #test_num ;*** next tests' number +2404 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; shifts - zeropage +2407 : a203 ldx #3 +2409 : tasl2 + set_z zp1,0 + > load_flag 0 +2409 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +240b : 48 > pha ;use stack to load status +240c : b513 > lda zp1,x ;load to zeropage +240e : 850c > sta zpt +2410 : 28 > plp + +2411 : 060c asl zpt + tst_z rASL,fASL,0 +2413 : 08 > php ;save flags +2414 : a50c > lda zpt +2416 : dd2002 > cmp rASL,x ;test result + > trap_ne +2419 : d0fe > bne * ;failed not equal (non zero) + > +241b : 68 > pla ;load status + > eor_flag 0 +241c : 4930 > eor #0|fao ;invert expected flags + always on bits + > +241e : dd3002 > cmp fASL,x ;test flags + > trap_ne +2421 : d0fe > bne * ;failed not equal (non zero) + > + +2423 : ca dex +2424 : 10e3 bpl tasl2 +2426 : a203 ldx #3 +2428 : tasl3 + set_z zp1,$ff + > load_flag $ff +2428 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +242a : 48 > pha ;use stack to load status +242b : b513 > lda zp1,x ;load to zeropage +242d : 850c > sta zpt +242f : 28 > plp + +2430 : 060c asl zpt + tst_z rASL,fASL,$ff-fnzc +2432 : 08 > php ;save flags +2433 : a50c > lda zpt +2435 : dd2002 > cmp rASL,x ;test result + > trap_ne +2438 : d0fe > bne * ;failed not equal (non zero) + > +243a : 68 > pla ;load status + > eor_flag $ff-fnzc +243b : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +243d : dd3002 > cmp fASL,x ;test flags + > trap_ne +2440 : d0fe > bne * ;failed not equal (non zero) + > + +2442 : ca dex +2443 : 10e3 bpl tasl3 + +2445 : a203 ldx #3 +2447 : tlsr2 + set_z zp1,0 + > load_flag 0 +2447 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2449 : 48 > pha ;use stack to load status +244a : b513 > lda zp1,x ;load to zeropage +244c : 850c > sta zpt +244e : 28 > plp + +244f : 460c lsr zpt + tst_z rLSR,fLSR,0 +2451 : 08 > php ;save flags +2452 : a50c > lda zpt +2454 : dd2802 > cmp rLSR,x ;test result + > trap_ne +2457 : d0fe > bne * ;failed not equal (non zero) + > +2459 : 68 > pla ;load status + > eor_flag 0 +245a : 4930 > eor #0|fao ;invert expected flags + always on bits + > +245c : dd3802 > cmp fLSR,x ;test flags + > trap_ne +245f : d0fe > bne * ;failed not equal (non zero) + > + +2461 : ca dex +2462 : 10e3 bpl tlsr2 +2464 : a203 ldx #3 +2466 : tlsr3 + set_z zp1,$ff + > load_flag $ff +2466 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2468 : 48 > pha ;use stack to load status +2469 : b513 > lda zp1,x ;load to zeropage +246b : 850c > sta zpt +246d : 28 > plp + +246e : 460c lsr zpt + tst_z rLSR,fLSR,$ff-fnzc +2470 : 08 > php ;save flags +2471 : a50c > lda zpt +2473 : dd2802 > cmp rLSR,x ;test result + > trap_ne +2476 : d0fe > bne * ;failed not equal (non zero) + > +2478 : 68 > pla ;load status + > eor_flag $ff-fnzc +2479 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +247b : dd3802 > cmp fLSR,x ;test flags + > trap_ne +247e : d0fe > bne * ;failed not equal (non zero) + > + +2480 : ca dex +2481 : 10e3 bpl tlsr3 + +2483 : a203 ldx #3 +2485 : trol2 + set_z zp1,0 + > load_flag 0 +2485 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2487 : 48 > pha ;use stack to load status +2488 : b513 > lda zp1,x ;load to zeropage +248a : 850c > sta zpt +248c : 28 > plp + +248d : 260c rol zpt + tst_z rROL,fROL,0 +248f : 08 > php ;save flags +2490 : a50c > lda zpt +2492 : dd2002 > cmp rROL,x ;test result + > trap_ne +2495 : d0fe > bne * ;failed not equal (non zero) + > +2497 : 68 > pla ;load status + > eor_flag 0 +2498 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +249a : dd3002 > cmp fROL,x ;test flags + > trap_ne +249d : d0fe > bne * ;failed not equal (non zero) + > + +249f : ca dex +24a0 : 10e3 bpl trol2 +24a2 : a203 ldx #3 +24a4 : trol3 + set_z zp1,$ff-fc + > load_flag $ff-fc +24a4 : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) + > +24a6 : 48 > pha ;use stack to load status +24a7 : b513 > lda zp1,x ;load to zeropage +24a9 : 850c > sta zpt +24ab : 28 > plp + +24ac : 260c rol zpt + tst_z rROL,fROL,$ff-fnzc +24ae : 08 > php ;save flags +24af : a50c > lda zpt +24b1 : dd2002 > cmp rROL,x ;test result + > trap_ne +24b4 : d0fe > bne * ;failed not equal (non zero) + > +24b6 : 68 > pla ;load status + > eor_flag $ff-fnzc +24b7 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +24b9 : dd3002 > cmp fROL,x ;test flags + > trap_ne +24bc : d0fe > bne * ;failed not equal (non zero) + > + +24be : ca dex +24bf : 10e3 bpl trol3 + +24c1 : a203 ldx #3 +24c3 : trolc2 + set_z zp1,fc + > load_flag fc +24c3 : a901 > lda #fc ;allow test to change I-flag (no mask) + > +24c5 : 48 > pha ;use stack to load status +24c6 : b513 > lda zp1,x ;load to zeropage +24c8 : 850c > sta zpt +24ca : 28 > plp + +24cb : 260c rol zpt + tst_z rROLc,fROLc,0 +24cd : 08 > php ;save flags +24ce : a50c > lda zpt +24d0 : dd2402 > cmp rROLc,x ;test result + > trap_ne +24d3 : d0fe > bne * ;failed not equal (non zero) + > +24d5 : 68 > pla ;load status + > eor_flag 0 +24d6 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +24d8 : dd3402 > cmp fROLc,x ;test flags + > trap_ne +24db : d0fe > bne * ;failed not equal (non zero) + > + +24dd : ca dex +24de : 10e3 bpl trolc2 +24e0 : a203 ldx #3 +24e2 : trolc3 + set_z zp1,$ff + > load_flag $ff +24e2 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +24e4 : 48 > pha ;use stack to load status +24e5 : b513 > lda zp1,x ;load to zeropage +24e7 : 850c > sta zpt +24e9 : 28 > plp + +24ea : 260c rol zpt + tst_z rROLc,fROLc,$ff-fnzc +24ec : 08 > php ;save flags +24ed : a50c > lda zpt +24ef : dd2402 > cmp rROLc,x ;test result + > trap_ne +24f2 : d0fe > bne * ;failed not equal (non zero) + > +24f4 : 68 > pla ;load status + > eor_flag $ff-fnzc +24f5 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +24f7 : dd3402 > cmp fROLc,x ;test flags + > trap_ne +24fa : d0fe > bne * ;failed not equal (non zero) + > + +24fc : ca dex +24fd : 10e3 bpl trolc3 + +24ff : a203 ldx #3 +2501 : tror2 + set_z zp1,0 + > load_flag 0 +2501 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2503 : 48 > pha ;use stack to load status +2504 : b513 > lda zp1,x ;load to zeropage +2506 : 850c > sta zpt +2508 : 28 > plp + +2509 : 660c ror zpt + tst_z rROR,fROR,0 +250b : 08 > php ;save flags +250c : a50c > lda zpt +250e : dd2802 > cmp rROR,x ;test result + > trap_ne +2511 : d0fe > bne * ;failed not equal (non zero) + > +2513 : 68 > pla ;load status + > eor_flag 0 +2514 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2516 : dd3802 > cmp fROR,x ;test flags + > trap_ne +2519 : d0fe > bne * ;failed not equal (non zero) + > + +251b : ca dex +251c : 10e3 bpl tror2 +251e : a203 ldx #3 +2520 : tror3 + set_z zp1,$ff-fc + > load_flag $ff-fc +2520 : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) + > +2522 : 48 > pha ;use stack to load status +2523 : b513 > lda zp1,x ;load to zeropage +2525 : 850c > sta zpt +2527 : 28 > plp + +2528 : 660c ror zpt + tst_z rROR,fROR,$ff-fnzc +252a : 08 > php ;save flags +252b : a50c > lda zpt +252d : dd2802 > cmp rROR,x ;test result + > trap_ne +2530 : d0fe > bne * ;failed not equal (non zero) + > +2532 : 68 > pla ;load status + > eor_flag $ff-fnzc +2533 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +2535 : dd3802 > cmp fROR,x ;test flags + > trap_ne +2538 : d0fe > bne * ;failed not equal (non zero) + > + +253a : ca dex +253b : 10e3 bpl tror3 + +253d : a203 ldx #3 +253f : trorc2 + set_z zp1,fc + > load_flag fc +253f : a901 > lda #fc ;allow test to change I-flag (no mask) + > +2541 : 48 > pha ;use stack to load status +2542 : b513 > lda zp1,x ;load to zeropage +2544 : 850c > sta zpt +2546 : 28 > plp + +2547 : 660c ror zpt + tst_z rRORc,fRORc,0 +2549 : 08 > php ;save flags +254a : a50c > lda zpt +254c : dd2c02 > cmp rRORc,x ;test result + > trap_ne +254f : d0fe > bne * ;failed not equal (non zero) + > +2551 : 68 > pla ;load status + > eor_flag 0 +2552 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2554 : dd3c02 > cmp fRORc,x ;test flags + > trap_ne +2557 : d0fe > bne * ;failed not equal (non zero) + > + +2559 : ca dex +255a : 10e3 bpl trorc2 +255c : a203 ldx #3 +255e : trorc3 + set_z zp1,$ff + > load_flag $ff +255e : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2560 : 48 > pha ;use stack to load status +2561 : b513 > lda zp1,x ;load to zeropage +2563 : 850c > sta zpt +2565 : 28 > plp + +2566 : 660c ror zpt + tst_z rRORc,fRORc,$ff-fnzc +2568 : 08 > php ;save flags +2569 : a50c > lda zpt +256b : dd2c02 > cmp rRORc,x ;test result + > trap_ne +256e : d0fe > bne * ;failed not equal (non zero) + > +2570 : 68 > pla ;load status + > eor_flag $ff-fnzc +2571 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +2573 : dd3c02 > cmp fRORc,x ;test flags + > trap_ne +2576 : d0fe > bne * ;failed not equal (non zero) + > + +2578 : ca dex +2579 : 10e3 bpl trorc3 + next_test +257b : ad0002 > lda test_case ;previous test +257e : c91e > cmp #test_num + > trap_ne ;test is out of sequence +2580 : d0fe > bne * ;failed not equal (non zero) + > +001f = >test_num = test_num + 1 +2582 : a91f > lda #test_num ;*** next tests' number +2584 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; shifts - absolute +2587 : a203 ldx #3 +2589 : tasl4 + set_abs zp1,0 + > load_flag 0 +2589 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +258b : 48 > pha ;use stack to load status +258c : b513 > lda zp1,x ;load to memory +258e : 8d0302 > sta abst +2591 : 28 > plp + +2592 : 0e0302 asl abst + tst_abs rASL,fASL,0 +2595 : 08 > php ;save flags +2596 : ad0302 > lda abst +2599 : dd2002 > cmp rASL,x ;test result + > trap_ne +259c : d0fe > bne * ;failed not equal (non zero) + > +259e : 68 > pla ;load status + > eor_flag 0 +259f : 4930 > eor #0|fao ;invert expected flags + always on bits + > +25a1 : dd3002 > cmp fASL,x ;test flags + > trap_ne +25a4 : d0fe > bne * ;failed not equal (non zero) + > + +25a6 : ca dex +25a7 : 10e0 bpl tasl4 +25a9 : a203 ldx #3 +25ab : tasl5 + set_abs zp1,$ff + > load_flag $ff +25ab : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +25ad : 48 > pha ;use stack to load status +25ae : b513 > lda zp1,x ;load to memory +25b0 : 8d0302 > sta abst +25b3 : 28 > plp + +25b4 : 0e0302 asl abst + tst_abs rASL,fASL,$ff-fnzc +25b7 : 08 > php ;save flags +25b8 : ad0302 > lda abst +25bb : dd2002 > cmp rASL,x ;test result + > trap_ne +25be : d0fe > bne * ;failed not equal (non zero) + > +25c0 : 68 > pla ;load status + > eor_flag $ff-fnzc +25c1 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +25c3 : dd3002 > cmp fASL,x ;test flags + > trap_ne +25c6 : d0fe > bne * ;failed not equal (non zero) + > + +25c8 : ca dex +25c9 : 10e0 bpl tasl5 + +25cb : a203 ldx #3 +25cd : tlsr4 + set_abs zp1,0 + > load_flag 0 +25cd : a900 > lda #0 ;allow test to change I-flag (no mask) + > +25cf : 48 > pha ;use stack to load status +25d0 : b513 > lda zp1,x ;load to memory +25d2 : 8d0302 > sta abst +25d5 : 28 > plp + +25d6 : 4e0302 lsr abst + tst_abs rLSR,fLSR,0 +25d9 : 08 > php ;save flags +25da : ad0302 > lda abst +25dd : dd2802 > cmp rLSR,x ;test result + > trap_ne +25e0 : d0fe > bne * ;failed not equal (non zero) + > +25e2 : 68 > pla ;load status + > eor_flag 0 +25e3 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +25e5 : dd3802 > cmp fLSR,x ;test flags + > trap_ne +25e8 : d0fe > bne * ;failed not equal (non zero) + > + +25ea : ca dex +25eb : 10e0 bpl tlsr4 +25ed : a203 ldx #3 +25ef : tlsr5 + set_abs zp1,$ff + > load_flag $ff +25ef : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +25f1 : 48 > pha ;use stack to load status +25f2 : b513 > lda zp1,x ;load to memory +25f4 : 8d0302 > sta abst +25f7 : 28 > plp + +25f8 : 4e0302 lsr abst + tst_abs rLSR,fLSR,$ff-fnzc +25fb : 08 > php ;save flags +25fc : ad0302 > lda abst +25ff : dd2802 > cmp rLSR,x ;test result + > trap_ne +2602 : d0fe > bne * ;failed not equal (non zero) + > +2604 : 68 > pla ;load status + > eor_flag $ff-fnzc +2605 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +2607 : dd3802 > cmp fLSR,x ;test flags + > trap_ne +260a : d0fe > bne * ;failed not equal (non zero) + > + +260c : ca dex +260d : 10e0 bpl tlsr5 + +260f : a203 ldx #3 +2611 : trol4 + set_abs zp1,0 + > load_flag 0 +2611 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2613 : 48 > pha ;use stack to load status +2614 : b513 > lda zp1,x ;load to memory +2616 : 8d0302 > sta abst +2619 : 28 > plp + +261a : 2e0302 rol abst + tst_abs rROL,fROL,0 +261d : 08 > php ;save flags +261e : ad0302 > lda abst +2621 : dd2002 > cmp rROL,x ;test result + > trap_ne +2624 : d0fe > bne * ;failed not equal (non zero) + > +2626 : 68 > pla ;load status + > eor_flag 0 +2627 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2629 : dd3002 > cmp fROL,x ;test flags + > trap_ne +262c : d0fe > bne * ;failed not equal (non zero) + > + +262e : ca dex +262f : 10e0 bpl trol4 +2631 : a203 ldx #3 +2633 : trol5 + set_abs zp1,$ff-fc + > load_flag $ff-fc +2633 : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) + > +2635 : 48 > pha ;use stack to load status +2636 : b513 > lda zp1,x ;load to memory +2638 : 8d0302 > sta abst +263b : 28 > plp + +263c : 2e0302 rol abst + tst_abs rROL,fROL,$ff-fnzc +263f : 08 > php ;save flags +2640 : ad0302 > lda abst +2643 : dd2002 > cmp rROL,x ;test result + > trap_ne +2646 : d0fe > bne * ;failed not equal (non zero) + > +2648 : 68 > pla ;load status + > eor_flag $ff-fnzc +2649 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +264b : dd3002 > cmp fROL,x ;test flags + > trap_ne +264e : d0fe > bne * ;failed not equal (non zero) + > + +2650 : ca dex +2651 : 10e0 bpl trol5 + +2653 : a203 ldx #3 +2655 : trolc4 + set_abs zp1,fc + > load_flag fc +2655 : a901 > lda #fc ;allow test to change I-flag (no mask) + > +2657 : 48 > pha ;use stack to load status +2658 : b513 > lda zp1,x ;load to memory +265a : 8d0302 > sta abst +265d : 28 > plp + +265e : 2e0302 rol abst + tst_abs rROLc,fROLc,0 +2661 : 08 > php ;save flags +2662 : ad0302 > lda abst +2665 : dd2402 > cmp rROLc,x ;test result + > trap_ne +2668 : d0fe > bne * ;failed not equal (non zero) + > +266a : 68 > pla ;load status + > eor_flag 0 +266b : 4930 > eor #0|fao ;invert expected flags + always on bits + > +266d : dd3402 > cmp fROLc,x ;test flags + > trap_ne +2670 : d0fe > bne * ;failed not equal (non zero) + > + +2672 : ca dex +2673 : 10e0 bpl trolc4 +2675 : a203 ldx #3 +2677 : trolc5 + set_abs zp1,$ff + > load_flag $ff +2677 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2679 : 48 > pha ;use stack to load status +267a : b513 > lda zp1,x ;load to memory +267c : 8d0302 > sta abst +267f : 28 > plp + +2680 : 2e0302 rol abst + tst_abs rROLc,fROLc,$ff-fnzc +2683 : 08 > php ;save flags +2684 : ad0302 > lda abst +2687 : dd2402 > cmp rROLc,x ;test result + > trap_ne +268a : d0fe > bne * ;failed not equal (non zero) + > +268c : 68 > pla ;load status + > eor_flag $ff-fnzc +268d : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +268f : dd3402 > cmp fROLc,x ;test flags + > trap_ne +2692 : d0fe > bne * ;failed not equal (non zero) + > + +2694 : ca dex +2695 : 10e0 bpl trolc5 + +2697 : a203 ldx #3 +2699 : tror4 + set_abs zp1,0 + > load_flag 0 +2699 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +269b : 48 > pha ;use stack to load status +269c : b513 > lda zp1,x ;load to memory +269e : 8d0302 > sta abst +26a1 : 28 > plp + +26a2 : 6e0302 ror abst + tst_abs rROR,fROR,0 +26a5 : 08 > php ;save flags +26a6 : ad0302 > lda abst +26a9 : dd2802 > cmp rROR,x ;test result + > trap_ne +26ac : d0fe > bne * ;failed not equal (non zero) + > +26ae : 68 > pla ;load status + > eor_flag 0 +26af : 4930 > eor #0|fao ;invert expected flags + always on bits + > +26b1 : dd3802 > cmp fROR,x ;test flags + > trap_ne +26b4 : d0fe > bne * ;failed not equal (non zero) + > + +26b6 : ca dex +26b7 : 10e0 bpl tror4 +26b9 : a203 ldx #3 +26bb : tror5 + set_abs zp1,$ff-fc + > load_flag $ff-fc +26bb : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) + > +26bd : 48 > pha ;use stack to load status +26be : b513 > lda zp1,x ;load to memory +26c0 : 8d0302 > sta abst +26c3 : 28 > plp + +26c4 : 6e0302 ror abst + tst_abs rROR,fROR,$ff-fnzc +26c7 : 08 > php ;save flags +26c8 : ad0302 > lda abst +26cb : dd2802 > cmp rROR,x ;test result + > trap_ne +26ce : d0fe > bne * ;failed not equal (non zero) + > +26d0 : 68 > pla ;load status + > eor_flag $ff-fnzc +26d1 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +26d3 : dd3802 > cmp fROR,x ;test flags + > trap_ne +26d6 : d0fe > bne * ;failed not equal (non zero) + > + +26d8 : ca dex +26d9 : 10e0 bpl tror5 + +26db : a203 ldx #3 +26dd : trorc4 + set_abs zp1,fc + > load_flag fc +26dd : a901 > lda #fc ;allow test to change I-flag (no mask) + > +26df : 48 > pha ;use stack to load status +26e0 : b513 > lda zp1,x ;load to memory +26e2 : 8d0302 > sta abst +26e5 : 28 > plp + +26e6 : 6e0302 ror abst + tst_abs rRORc,fRORc,0 +26e9 : 08 > php ;save flags +26ea : ad0302 > lda abst +26ed : dd2c02 > cmp rRORc,x ;test result + > trap_ne +26f0 : d0fe > bne * ;failed not equal (non zero) + > +26f2 : 68 > pla ;load status + > eor_flag 0 +26f3 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +26f5 : dd3c02 > cmp fRORc,x ;test flags + > trap_ne +26f8 : d0fe > bne * ;failed not equal (non zero) + > + +26fa : ca dex +26fb : 10e0 bpl trorc4 +26fd : a203 ldx #3 +26ff : trorc5 + set_abs zp1,$ff + > load_flag $ff +26ff : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2701 : 48 > pha ;use stack to load status +2702 : b513 > lda zp1,x ;load to memory +2704 : 8d0302 > sta abst +2707 : 28 > plp + +2708 : 6e0302 ror abst + tst_abs rRORc,fRORc,$ff-fnzc +270b : 08 > php ;save flags +270c : ad0302 > lda abst +270f : dd2c02 > cmp rRORc,x ;test result + > trap_ne +2712 : d0fe > bne * ;failed not equal (non zero) + > +2714 : 68 > pla ;load status + > eor_flag $ff-fnzc +2715 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +2717 : dd3c02 > cmp fRORc,x ;test flags + > trap_ne +271a : d0fe > bne * ;failed not equal (non zero) + > + +271c : ca dex +271d : 10e0 bpl trorc5 + next_test +271f : ad0002 > lda test_case ;previous test +2722 : c91f > cmp #test_num + > trap_ne ;test is out of sequence +2724 : d0fe > bne * ;failed not equal (non zero) + > +0020 = >test_num = test_num + 1 +2726 : a920 > lda #test_num ;*** next tests' number +2728 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; shifts - zp indexed +272b : a203 ldx #3 +272d : tasl6 + set_zx zp1,0 + > load_flag 0 +272d : a900 > lda #0 ;allow test to change I-flag (no mask) + > +272f : 48 > pha ;use stack to load status +2730 : b513 > lda zp1,x ;load to indexed zeropage +2732 : 950c > sta zpt,x +2734 : 28 > plp + +2735 : 160c asl zpt,x + tst_zx rASL,fASL,0 +2737 : 08 > php ;save flags +2738 : b50c > lda zpt,x +273a : dd2002 > cmp rASL,x ;test result + > trap_ne +273d : d0fe > bne * ;failed not equal (non zero) + > +273f : 68 > pla ;load status + > eor_flag 0 +2740 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2742 : dd3002 > cmp fASL,x ;test flags + > trap_ne +2745 : d0fe > bne * ;failed not equal (non zero) + > + +2747 : ca dex +2748 : 10e3 bpl tasl6 +274a : a203 ldx #3 +274c : tasl7 + set_zx zp1,$ff + > load_flag $ff +274c : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +274e : 48 > pha ;use stack to load status +274f : b513 > lda zp1,x ;load to indexed zeropage +2751 : 950c > sta zpt,x +2753 : 28 > plp + +2754 : 160c asl zpt,x + tst_zx rASL,fASL,$ff-fnzc +2756 : 08 > php ;save flags +2757 : b50c > lda zpt,x +2759 : dd2002 > cmp rASL,x ;test result + > trap_ne +275c : d0fe > bne * ;failed not equal (non zero) + > +275e : 68 > pla ;load status + > eor_flag $ff-fnzc +275f : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +2761 : dd3002 > cmp fASL,x ;test flags + > trap_ne +2764 : d0fe > bne * ;failed not equal (non zero) + > + +2766 : ca dex +2767 : 10e3 bpl tasl7 + +2769 : a203 ldx #3 +276b : tlsr6 + set_zx zp1,0 + > load_flag 0 +276b : a900 > lda #0 ;allow test to change I-flag (no mask) + > +276d : 48 > pha ;use stack to load status +276e : b513 > lda zp1,x ;load to indexed zeropage +2770 : 950c > sta zpt,x +2772 : 28 > plp + +2773 : 560c lsr zpt,x + tst_zx rLSR,fLSR,0 +2775 : 08 > php ;save flags +2776 : b50c > lda zpt,x +2778 : dd2802 > cmp rLSR,x ;test result + > trap_ne +277b : d0fe > bne * ;failed not equal (non zero) + > +277d : 68 > pla ;load status + > eor_flag 0 +277e : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2780 : dd3802 > cmp fLSR,x ;test flags + > trap_ne +2783 : d0fe > bne * ;failed not equal (non zero) + > + +2785 : ca dex +2786 : 10e3 bpl tlsr6 +2788 : a203 ldx #3 +278a : tlsr7 + set_zx zp1,$ff + > load_flag $ff +278a : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +278c : 48 > pha ;use stack to load status +278d : b513 > lda zp1,x ;load to indexed zeropage +278f : 950c > sta zpt,x +2791 : 28 > plp + +2792 : 560c lsr zpt,x + tst_zx rLSR,fLSR,$ff-fnzc +2794 : 08 > php ;save flags +2795 : b50c > lda zpt,x +2797 : dd2802 > cmp rLSR,x ;test result + > trap_ne +279a : d0fe > bne * ;failed not equal (non zero) + > +279c : 68 > pla ;load status + > eor_flag $ff-fnzc +279d : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +279f : dd3802 > cmp fLSR,x ;test flags + > trap_ne +27a2 : d0fe > bne * ;failed not equal (non zero) + > + +27a4 : ca dex +27a5 : 10e3 bpl tlsr7 + +27a7 : a203 ldx #3 +27a9 : trol6 + set_zx zp1,0 + > load_flag 0 +27a9 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +27ab : 48 > pha ;use stack to load status +27ac : b513 > lda zp1,x ;load to indexed zeropage +27ae : 950c > sta zpt,x +27b0 : 28 > plp + +27b1 : 360c rol zpt,x + tst_zx rROL,fROL,0 +27b3 : 08 > php ;save flags +27b4 : b50c > lda zpt,x +27b6 : dd2002 > cmp rROL,x ;test result + > trap_ne +27b9 : d0fe > bne * ;failed not equal (non zero) + > +27bb : 68 > pla ;load status + > eor_flag 0 +27bc : 4930 > eor #0|fao ;invert expected flags + always on bits + > +27be : dd3002 > cmp fROL,x ;test flags + > trap_ne +27c1 : d0fe > bne * ;failed not equal (non zero) + > + +27c3 : ca dex +27c4 : 10e3 bpl trol6 +27c6 : a203 ldx #3 +27c8 : trol7 + set_zx zp1,$ff-fc + > load_flag $ff-fc +27c8 : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) + > +27ca : 48 > pha ;use stack to load status +27cb : b513 > lda zp1,x ;load to indexed zeropage +27cd : 950c > sta zpt,x +27cf : 28 > plp + +27d0 : 360c rol zpt,x + tst_zx rROL,fROL,$ff-fnzc +27d2 : 08 > php ;save flags +27d3 : b50c > lda zpt,x +27d5 : dd2002 > cmp rROL,x ;test result + > trap_ne +27d8 : d0fe > bne * ;failed not equal (non zero) + > +27da : 68 > pla ;load status + > eor_flag $ff-fnzc +27db : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +27dd : dd3002 > cmp fROL,x ;test flags + > trap_ne +27e0 : d0fe > bne * ;failed not equal (non zero) + > + +27e2 : ca dex +27e3 : 10e3 bpl trol7 + +27e5 : a203 ldx #3 +27e7 : trolc6 + set_zx zp1,fc + > load_flag fc +27e7 : a901 > lda #fc ;allow test to change I-flag (no mask) + > +27e9 : 48 > pha ;use stack to load status +27ea : b513 > lda zp1,x ;load to indexed zeropage +27ec : 950c > sta zpt,x +27ee : 28 > plp + +27ef : 360c rol zpt,x + tst_zx rROLc,fROLc,0 +27f1 : 08 > php ;save flags +27f2 : b50c > lda zpt,x +27f4 : dd2402 > cmp rROLc,x ;test result + > trap_ne +27f7 : d0fe > bne * ;failed not equal (non zero) + > +27f9 : 68 > pla ;load status + > eor_flag 0 +27fa : 4930 > eor #0|fao ;invert expected flags + always on bits + > +27fc : dd3402 > cmp fROLc,x ;test flags + > trap_ne +27ff : d0fe > bne * ;failed not equal (non zero) + > + +2801 : ca dex +2802 : 10e3 bpl trolc6 +2804 : a203 ldx #3 +2806 : trolc7 + set_zx zp1,$ff + > load_flag $ff +2806 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2808 : 48 > pha ;use stack to load status +2809 : b513 > lda zp1,x ;load to indexed zeropage +280b : 950c > sta zpt,x +280d : 28 > plp + +280e : 360c rol zpt,x + tst_zx rROLc,fROLc,$ff-fnzc +2810 : 08 > php ;save flags +2811 : b50c > lda zpt,x +2813 : dd2402 > cmp rROLc,x ;test result + > trap_ne +2816 : d0fe > bne * ;failed not equal (non zero) + > +2818 : 68 > pla ;load status + > eor_flag $ff-fnzc +2819 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +281b : dd3402 > cmp fROLc,x ;test flags + > trap_ne +281e : d0fe > bne * ;failed not equal (non zero) + > + +2820 : ca dex +2821 : 10e3 bpl trolc7 + +2823 : a203 ldx #3 +2825 : tror6 + set_zx zp1,0 + > load_flag 0 +2825 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2827 : 48 > pha ;use stack to load status +2828 : b513 > lda zp1,x ;load to indexed zeropage +282a : 950c > sta zpt,x +282c : 28 > plp + +282d : 760c ror zpt,x + tst_zx rROR,fROR,0 +282f : 08 > php ;save flags +2830 : b50c > lda zpt,x +2832 : dd2802 > cmp rROR,x ;test result + > trap_ne +2835 : d0fe > bne * ;failed not equal (non zero) + > +2837 : 68 > pla ;load status + > eor_flag 0 +2838 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +283a : dd3802 > cmp fROR,x ;test flags + > trap_ne +283d : d0fe > bne * ;failed not equal (non zero) + > + +283f : ca dex +2840 : 10e3 bpl tror6 +2842 : a203 ldx #3 +2844 : tror7 + set_zx zp1,$ff-fc + > load_flag $ff-fc +2844 : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) + > +2846 : 48 > pha ;use stack to load status +2847 : b513 > lda zp1,x ;load to indexed zeropage +2849 : 950c > sta zpt,x +284b : 28 > plp + +284c : 760c ror zpt,x + tst_zx rROR,fROR,$ff-fnzc +284e : 08 > php ;save flags +284f : b50c > lda zpt,x +2851 : dd2802 > cmp rROR,x ;test result + > trap_ne +2854 : d0fe > bne * ;failed not equal (non zero) + > +2856 : 68 > pla ;load status + > eor_flag $ff-fnzc +2857 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +2859 : dd3802 > cmp fROR,x ;test flags + > trap_ne +285c : d0fe > bne * ;failed not equal (non zero) + > + +285e : ca dex +285f : 10e3 bpl tror7 + +2861 : a203 ldx #3 +2863 : trorc6 + set_zx zp1,fc + > load_flag fc +2863 : a901 > lda #fc ;allow test to change I-flag (no mask) + > +2865 : 48 > pha ;use stack to load status +2866 : b513 > lda zp1,x ;load to indexed zeropage +2868 : 950c > sta zpt,x +286a : 28 > plp + +286b : 760c ror zpt,x + tst_zx rRORc,fRORc,0 +286d : 08 > php ;save flags +286e : b50c > lda zpt,x +2870 : dd2c02 > cmp rRORc,x ;test result + > trap_ne +2873 : d0fe > bne * ;failed not equal (non zero) + > +2875 : 68 > pla ;load status + > eor_flag 0 +2876 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2878 : dd3c02 > cmp fRORc,x ;test flags + > trap_ne +287b : d0fe > bne * ;failed not equal (non zero) + > + +287d : ca dex +287e : 10e3 bpl trorc6 +2880 : a203 ldx #3 +2882 : trorc7 + set_zx zp1,$ff + > load_flag $ff +2882 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2884 : 48 > pha ;use stack to load status +2885 : b513 > lda zp1,x ;load to indexed zeropage +2887 : 950c > sta zpt,x +2889 : 28 > plp + +288a : 760c ror zpt,x + tst_zx rRORc,fRORc,$ff-fnzc +288c : 08 > php ;save flags +288d : b50c > lda zpt,x +288f : dd2c02 > cmp rRORc,x ;test result + > trap_ne +2892 : d0fe > bne * ;failed not equal (non zero) + > +2894 : 68 > pla ;load status + > eor_flag $ff-fnzc +2895 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +2897 : dd3c02 > cmp fRORc,x ;test flags + > trap_ne +289a : d0fe > bne * ;failed not equal (non zero) + > + +289c : ca dex +289d : 10e3 bpl trorc7 + next_test +289f : ad0002 > lda test_case ;previous test +28a2 : c920 > cmp #test_num + > trap_ne ;test is out of sequence +28a4 : d0fe > bne * ;failed not equal (non zero) + > +0021 = >test_num = test_num + 1 +28a6 : a921 > lda #test_num ;*** next tests' number +28a8 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; shifts - abs indexed +28ab : a203 ldx #3 +28ad : tasl8 + set_absx zp1,0 + > load_flag 0 +28ad : a900 > lda #0 ;allow test to change I-flag (no mask) + > +28af : 48 > pha ;use stack to load status +28b0 : b513 > lda zp1,x ;load to indexed memory +28b2 : 9d0302 > sta abst,x +28b5 : 28 > plp + +28b6 : 1e0302 asl abst,x + tst_absx rASL,fASL,0 +28b9 : 08 > php ;save flags +28ba : bd0302 > lda abst,x +28bd : dd2002 > cmp rASL,x ;test result + > trap_ne +28c0 : d0fe > bne * ;failed not equal (non zero) + > +28c2 : 68 > pla ;load status + > eor_flag 0 +28c3 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +28c5 : dd3002 > cmp fASL,x ;test flags + > trap_ne +28c8 : d0fe > bne * ;failed not equal (non zero) + > + +28ca : ca dex +28cb : 10e0 bpl tasl8 +28cd : a203 ldx #3 +28cf : tasl9 + set_absx zp1,$ff + > load_flag $ff +28cf : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +28d1 : 48 > pha ;use stack to load status +28d2 : b513 > lda zp1,x ;load to indexed memory +28d4 : 9d0302 > sta abst,x +28d7 : 28 > plp + +28d8 : 1e0302 asl abst,x + tst_absx rASL,fASL,$ff-fnzc +28db : 08 > php ;save flags +28dc : bd0302 > lda abst,x +28df : dd2002 > cmp rASL,x ;test result + > trap_ne +28e2 : d0fe > bne * ;failed not equal (non zero) + > +28e4 : 68 > pla ;load status + > eor_flag $ff-fnzc +28e5 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +28e7 : dd3002 > cmp fASL,x ;test flags + > trap_ne +28ea : d0fe > bne * ;failed not equal (non zero) + > + +28ec : ca dex +28ed : 10e0 bpl tasl9 + +28ef : a203 ldx #3 +28f1 : tlsr8 + set_absx zp1,0 + > load_flag 0 +28f1 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +28f3 : 48 > pha ;use stack to load status +28f4 : b513 > lda zp1,x ;load to indexed memory +28f6 : 9d0302 > sta abst,x +28f9 : 28 > plp + +28fa : 5e0302 lsr abst,x + tst_absx rLSR,fLSR,0 +28fd : 08 > php ;save flags +28fe : bd0302 > lda abst,x +2901 : dd2802 > cmp rLSR,x ;test result + > trap_ne +2904 : d0fe > bne * ;failed not equal (non zero) + > +2906 : 68 > pla ;load status + > eor_flag 0 +2907 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2909 : dd3802 > cmp fLSR,x ;test flags + > trap_ne +290c : d0fe > bne * ;failed not equal (non zero) + > + +290e : ca dex +290f : 10e0 bpl tlsr8 +2911 : a203 ldx #3 +2913 : tlsr9 + set_absx zp1,$ff + > load_flag $ff +2913 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2915 : 48 > pha ;use stack to load status +2916 : b513 > lda zp1,x ;load to indexed memory +2918 : 9d0302 > sta abst,x +291b : 28 > plp + +291c : 5e0302 lsr abst,x + tst_absx rLSR,fLSR,$ff-fnzc +291f : 08 > php ;save flags +2920 : bd0302 > lda abst,x +2923 : dd2802 > cmp rLSR,x ;test result + > trap_ne +2926 : d0fe > bne * ;failed not equal (non zero) + > +2928 : 68 > pla ;load status + > eor_flag $ff-fnzc +2929 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +292b : dd3802 > cmp fLSR,x ;test flags + > trap_ne +292e : d0fe > bne * ;failed not equal (non zero) + > + +2930 : ca dex +2931 : 10e0 bpl tlsr9 + +2933 : a203 ldx #3 +2935 : trol8 + set_absx zp1,0 + > load_flag 0 +2935 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2937 : 48 > pha ;use stack to load status +2938 : b513 > lda zp1,x ;load to indexed memory +293a : 9d0302 > sta abst,x +293d : 28 > plp + +293e : 3e0302 rol abst,x + tst_absx rROL,fROL,0 +2941 : 08 > php ;save flags +2942 : bd0302 > lda abst,x +2945 : dd2002 > cmp rROL,x ;test result + > trap_ne +2948 : d0fe > bne * ;failed not equal (non zero) + > +294a : 68 > pla ;load status + > eor_flag 0 +294b : 4930 > eor #0|fao ;invert expected flags + always on bits + > +294d : dd3002 > cmp fROL,x ;test flags + > trap_ne +2950 : d0fe > bne * ;failed not equal (non zero) + > + +2952 : ca dex +2953 : 10e0 bpl trol8 +2955 : a203 ldx #3 +2957 : trol9 + set_absx zp1,$ff-fc + > load_flag $ff-fc +2957 : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) + > +2959 : 48 > pha ;use stack to load status +295a : b513 > lda zp1,x ;load to indexed memory +295c : 9d0302 > sta abst,x +295f : 28 > plp + +2960 : 3e0302 rol abst,x + tst_absx rROL,fROL,$ff-fnzc +2963 : 08 > php ;save flags +2964 : bd0302 > lda abst,x +2967 : dd2002 > cmp rROL,x ;test result + > trap_ne +296a : d0fe > bne * ;failed not equal (non zero) + > +296c : 68 > pla ;load status + > eor_flag $ff-fnzc +296d : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +296f : dd3002 > cmp fROL,x ;test flags + > trap_ne +2972 : d0fe > bne * ;failed not equal (non zero) + > + +2974 : ca dex +2975 : 10e0 bpl trol9 + +2977 : a203 ldx #3 +2979 : trolc8 + set_absx zp1,fc + > load_flag fc +2979 : a901 > lda #fc ;allow test to change I-flag (no mask) + > +297b : 48 > pha ;use stack to load status +297c : b513 > lda zp1,x ;load to indexed memory +297e : 9d0302 > sta abst,x +2981 : 28 > plp + +2982 : 3e0302 rol abst,x + tst_absx rROLc,fROLc,0 +2985 : 08 > php ;save flags +2986 : bd0302 > lda abst,x +2989 : dd2402 > cmp rROLc,x ;test result + > trap_ne +298c : d0fe > bne * ;failed not equal (non zero) + > +298e : 68 > pla ;load status + > eor_flag 0 +298f : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2991 : dd3402 > cmp fROLc,x ;test flags + > trap_ne +2994 : d0fe > bne * ;failed not equal (non zero) + > + +2996 : ca dex +2997 : 10e0 bpl trolc8 +2999 : a203 ldx #3 +299b : trolc9 + set_absx zp1,$ff + > load_flag $ff +299b : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +299d : 48 > pha ;use stack to load status +299e : b513 > lda zp1,x ;load to indexed memory +29a0 : 9d0302 > sta abst,x +29a3 : 28 > plp + +29a4 : 3e0302 rol abst,x + tst_absx rROLc,fROLc,$ff-fnzc +29a7 : 08 > php ;save flags +29a8 : bd0302 > lda abst,x +29ab : dd2402 > cmp rROLc,x ;test result + > trap_ne +29ae : d0fe > bne * ;failed not equal (non zero) + > +29b0 : 68 > pla ;load status + > eor_flag $ff-fnzc +29b1 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +29b3 : dd3402 > cmp fROLc,x ;test flags + > trap_ne +29b6 : d0fe > bne * ;failed not equal (non zero) + > + +29b8 : ca dex +29b9 : 10e0 bpl trolc9 + +29bb : a203 ldx #3 +29bd : tror8 + set_absx zp1,0 + > load_flag 0 +29bd : a900 > lda #0 ;allow test to change I-flag (no mask) + > +29bf : 48 > pha ;use stack to load status +29c0 : b513 > lda zp1,x ;load to indexed memory +29c2 : 9d0302 > sta abst,x +29c5 : 28 > plp + +29c6 : 7e0302 ror abst,x + tst_absx rROR,fROR,0 +29c9 : 08 > php ;save flags +29ca : bd0302 > lda abst,x +29cd : dd2802 > cmp rROR,x ;test result + > trap_ne +29d0 : d0fe > bne * ;failed not equal (non zero) + > +29d2 : 68 > pla ;load status + > eor_flag 0 +29d3 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +29d5 : dd3802 > cmp fROR,x ;test flags + > trap_ne +29d8 : d0fe > bne * ;failed not equal (non zero) + > + +29da : ca dex +29db : 10e0 bpl tror8 +29dd : a203 ldx #3 +29df : tror9 + set_absx zp1,$ff-fc + > load_flag $ff-fc +29df : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) + > +29e1 : 48 > pha ;use stack to load status +29e2 : b513 > lda zp1,x ;load to indexed memory +29e4 : 9d0302 > sta abst,x +29e7 : 28 > plp + +29e8 : 7e0302 ror abst,x + tst_absx rROR,fROR,$ff-fnzc +29eb : 08 > php ;save flags +29ec : bd0302 > lda abst,x +29ef : dd2802 > cmp rROR,x ;test result + > trap_ne +29f2 : d0fe > bne * ;failed not equal (non zero) + > +29f4 : 68 > pla ;load status + > eor_flag $ff-fnzc +29f5 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +29f7 : dd3802 > cmp fROR,x ;test flags + > trap_ne +29fa : d0fe > bne * ;failed not equal (non zero) + > + +29fc : ca dex +29fd : 10e0 bpl tror9 + +29ff : a203 ldx #3 +2a01 : trorc8 + set_absx zp1,fc + > load_flag fc +2a01 : a901 > lda #fc ;allow test to change I-flag (no mask) + > +2a03 : 48 > pha ;use stack to load status +2a04 : b513 > lda zp1,x ;load to indexed memory +2a06 : 9d0302 > sta abst,x +2a09 : 28 > plp + +2a0a : 7e0302 ror abst,x + tst_absx rRORc,fRORc,0 +2a0d : 08 > php ;save flags +2a0e : bd0302 > lda abst,x +2a11 : dd2c02 > cmp rRORc,x ;test result + > trap_ne +2a14 : d0fe > bne * ;failed not equal (non zero) + > +2a16 : 68 > pla ;load status + > eor_flag 0 +2a17 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2a19 : dd3c02 > cmp fRORc,x ;test flags + > trap_ne +2a1c : d0fe > bne * ;failed not equal (non zero) + > + +2a1e : ca dex +2a1f : 10e0 bpl trorc8 +2a21 : a203 ldx #3 +2a23 : trorc9 + set_absx zp1,$ff + > load_flag $ff +2a23 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2a25 : 48 > pha ;use stack to load status +2a26 : b513 > lda zp1,x ;load to indexed memory +2a28 : 9d0302 > sta abst,x +2a2b : 28 > plp + +2a2c : 7e0302 ror abst,x + tst_absx rRORc,fRORc,$ff-fnzc +2a2f : 08 > php ;save flags +2a30 : bd0302 > lda abst,x +2a33 : dd2c02 > cmp rRORc,x ;test result + > trap_ne +2a36 : d0fe > bne * ;failed not equal (non zero) + > +2a38 : 68 > pla ;load status + > eor_flag $ff-fnzc +2a39 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits + > +2a3b : dd3c02 > cmp fRORc,x ;test flags + > trap_ne +2a3e : d0fe > bne * ;failed not equal (non zero) + > + +2a40 : ca dex +2a41 : 10e0 bpl trorc9 + next_test +2a43 : ad0002 > lda test_case ;previous test +2a46 : c921 > cmp #test_num + > trap_ne ;test is out of sequence +2a48 : d0fe > bne * ;failed not equal (non zero) + > +0022 = >test_num = test_num + 1 +2a4a : a922 > lda #test_num ;*** next tests' number +2a4c : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; testing memory increment/decrement - INC DEC all addressing modes + ; zeropage +2a4f : a200 ldx #0 +2a51 : a97e lda #$7e +2a53 : 850c sta zpt +2a55 : tinc + set_stat 0 + > load_flag 0 +2a55 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2a57 : 48 > pha ;use stack to load status +2a58 : 28 > plp + +2a59 : e60c inc zpt + tst_z rINC,fINC,0 +2a5b : 08 > php ;save flags +2a5c : a50c > lda zpt +2a5e : dd4002 > cmp rINC,x ;test result + > trap_ne +2a61 : d0fe > bne * ;failed not equal (non zero) + > +2a63 : 68 > pla ;load status + > eor_flag 0 +2a64 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2a66 : dd4502 > cmp fINC,x ;test flags + > trap_ne +2a69 : d0fe > bne * ;failed not equal (non zero) + > + +2a6b : e8 inx +2a6c : e002 cpx #2 +2a6e : d004 bne tinc1 +2a70 : a9fe lda #$fe +2a72 : 850c sta zpt +2a74 : e005 tinc1 cpx #5 +2a76 : d0dd bne tinc +2a78 : ca dex +2a79 : e60c inc zpt +2a7b : tdec + set_stat 0 + > load_flag 0 +2a7b : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2a7d : 48 > pha ;use stack to load status +2a7e : 28 > plp + +2a7f : c60c dec zpt + tst_z rINC,fINC,0 +2a81 : 08 > php ;save flags +2a82 : a50c > lda zpt +2a84 : dd4002 > cmp rINC,x ;test result + > trap_ne +2a87 : d0fe > bne * ;failed not equal (non zero) + > +2a89 : 68 > pla ;load status + > eor_flag 0 +2a8a : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2a8c : dd4502 > cmp fINC,x ;test flags + > trap_ne +2a8f : d0fe > bne * ;failed not equal (non zero) + > + +2a91 : ca dex +2a92 : 300a bmi tdec1 +2a94 : e001 cpx #1 +2a96 : d0e3 bne tdec +2a98 : a981 lda #$81 +2a9a : 850c sta zpt +2a9c : d0dd bne tdec +2a9e : tdec1 +2a9e : a200 ldx #0 +2aa0 : a97e lda #$7e +2aa2 : 850c sta zpt +2aa4 : tinc10 + set_stat $ff + > load_flag $ff +2aa4 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2aa6 : 48 > pha ;use stack to load status +2aa7 : 28 > plp + +2aa8 : e60c inc zpt + tst_z rINC,fINC,$ff-fnz +2aaa : 08 > php ;save flags +2aab : a50c > lda zpt +2aad : dd4002 > cmp rINC,x ;test result + > trap_ne +2ab0 : d0fe > bne * ;failed not equal (non zero) + > +2ab2 : 68 > pla ;load status + > eor_flag $ff-fnz +2ab3 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +2ab5 : dd4502 > cmp fINC,x ;test flags + > trap_ne +2ab8 : d0fe > bne * ;failed not equal (non zero) + > + +2aba : e8 inx +2abb : e002 cpx #2 +2abd : d004 bne tinc11 +2abf : a9fe lda #$fe +2ac1 : 850c sta zpt +2ac3 : e005 tinc11 cpx #5 +2ac5 : d0dd bne tinc10 +2ac7 : ca dex +2ac8 : e60c inc zpt +2aca : tdec10 + set_stat $ff + > load_flag $ff +2aca : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2acc : 48 > pha ;use stack to load status +2acd : 28 > plp + +2ace : c60c dec zpt + tst_z rINC,fINC,$ff-fnz +2ad0 : 08 > php ;save flags +2ad1 : a50c > lda zpt +2ad3 : dd4002 > cmp rINC,x ;test result + > trap_ne +2ad6 : d0fe > bne * ;failed not equal (non zero) + > +2ad8 : 68 > pla ;load status + > eor_flag $ff-fnz +2ad9 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +2adb : dd4502 > cmp fINC,x ;test flags + > trap_ne +2ade : d0fe > bne * ;failed not equal (non zero) + > + +2ae0 : ca dex +2ae1 : 300a bmi tdec11 +2ae3 : e001 cpx #1 +2ae5 : d0e3 bne tdec10 +2ae7 : a981 lda #$81 +2ae9 : 850c sta zpt +2aeb : d0dd bne tdec10 +2aed : tdec11 + next_test +2aed : ad0002 > lda test_case ;previous test +2af0 : c922 > cmp #test_num + > trap_ne ;test is out of sequence +2af2 : d0fe > bne * ;failed not equal (non zero) + > +0023 = >test_num = test_num + 1 +2af4 : a923 > lda #test_num ;*** next tests' number +2af6 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; absolute memory +2af9 : a200 ldx #0 +2afb : a97e lda #$7e +2afd : 8d0302 sta abst +2b00 : tinc2 + set_stat 0 + > load_flag 0 +2b00 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2b02 : 48 > pha ;use stack to load status +2b03 : 28 > plp + +2b04 : ee0302 inc abst + tst_abs rINC,fINC,0 +2b07 : 08 > php ;save flags +2b08 : ad0302 > lda abst +2b0b : dd4002 > cmp rINC,x ;test result + > trap_ne +2b0e : d0fe > bne * ;failed not equal (non zero) + > +2b10 : 68 > pla ;load status + > eor_flag 0 +2b11 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2b13 : dd4502 > cmp fINC,x ;test flags + > trap_ne +2b16 : d0fe > bne * ;failed not equal (non zero) + > + +2b18 : e8 inx +2b19 : e002 cpx #2 +2b1b : d005 bne tinc3 +2b1d : a9fe lda #$fe +2b1f : 8d0302 sta abst +2b22 : e005 tinc3 cpx #5 +2b24 : d0da bne tinc2 +2b26 : ca dex +2b27 : ee0302 inc abst +2b2a : tdec2 + set_stat 0 + > load_flag 0 +2b2a : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2b2c : 48 > pha ;use stack to load status +2b2d : 28 > plp + +2b2e : ce0302 dec abst + tst_abs rINC,fINC,0 +2b31 : 08 > php ;save flags +2b32 : ad0302 > lda abst +2b35 : dd4002 > cmp rINC,x ;test result + > trap_ne +2b38 : d0fe > bne * ;failed not equal (non zero) + > +2b3a : 68 > pla ;load status + > eor_flag 0 +2b3b : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2b3d : dd4502 > cmp fINC,x ;test flags + > trap_ne +2b40 : d0fe > bne * ;failed not equal (non zero) + > + +2b42 : ca dex +2b43 : 300b bmi tdec3 +2b45 : e001 cpx #1 +2b47 : d0e1 bne tdec2 +2b49 : a981 lda #$81 +2b4b : 8d0302 sta abst +2b4e : d0da bne tdec2 +2b50 : tdec3 +2b50 : a200 ldx #0 +2b52 : a97e lda #$7e +2b54 : 8d0302 sta abst +2b57 : tinc12 + set_stat $ff + > load_flag $ff +2b57 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2b59 : 48 > pha ;use stack to load status +2b5a : 28 > plp + +2b5b : ee0302 inc abst + tst_abs rINC,fINC,$ff-fnz +2b5e : 08 > php ;save flags +2b5f : ad0302 > lda abst +2b62 : dd4002 > cmp rINC,x ;test result + > trap_ne +2b65 : d0fe > bne * ;failed not equal (non zero) + > +2b67 : 68 > pla ;load status + > eor_flag $ff-fnz +2b68 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +2b6a : dd4502 > cmp fINC,x ;test flags + > trap_ne +2b6d : d0fe > bne * ;failed not equal (non zero) + > + +2b6f : e8 inx +2b70 : e002 cpx #2 +2b72 : d005 bne tinc13 +2b74 : a9fe lda #$fe +2b76 : 8d0302 sta abst +2b79 : e005 tinc13 cpx #5 +2b7b : d0da bne tinc12 +2b7d : ca dex +2b7e : ee0302 inc abst +2b81 : tdec12 + set_stat $ff + > load_flag $ff +2b81 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2b83 : 48 > pha ;use stack to load status +2b84 : 28 > plp + +2b85 : ce0302 dec abst + tst_abs rINC,fINC,$ff-fnz +2b88 : 08 > php ;save flags +2b89 : ad0302 > lda abst +2b8c : dd4002 > cmp rINC,x ;test result + > trap_ne +2b8f : d0fe > bne * ;failed not equal (non zero) + > +2b91 : 68 > pla ;load status + > eor_flag $ff-fnz +2b92 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +2b94 : dd4502 > cmp fINC,x ;test flags + > trap_ne +2b97 : d0fe > bne * ;failed not equal (non zero) + > + +2b99 : ca dex +2b9a : 300b bmi tdec13 +2b9c : e001 cpx #1 +2b9e : d0e1 bne tdec12 +2ba0 : a981 lda #$81 +2ba2 : 8d0302 sta abst +2ba5 : d0da bne tdec12 +2ba7 : tdec13 + next_test +2ba7 : ad0002 > lda test_case ;previous test +2baa : c923 > cmp #test_num + > trap_ne ;test is out of sequence +2bac : d0fe > bne * ;failed not equal (non zero) + > +0024 = >test_num = test_num + 1 +2bae : a924 > lda #test_num ;*** next tests' number +2bb0 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; zeropage indexed +2bb3 : a200 ldx #0 +2bb5 : a97e lda #$7e +2bb7 : 950c tinc4 sta zpt,x + set_stat 0 + > load_flag 0 +2bb9 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2bbb : 48 > pha ;use stack to load status +2bbc : 28 > plp + +2bbd : f60c inc zpt,x + tst_zx rINC,fINC,0 +2bbf : 08 > php ;save flags +2bc0 : b50c > lda zpt,x +2bc2 : dd4002 > cmp rINC,x ;test result + > trap_ne +2bc5 : d0fe > bne * ;failed not equal (non zero) + > +2bc7 : 68 > pla ;load status + > eor_flag 0 +2bc8 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2bca : dd4502 > cmp fINC,x ;test flags + > trap_ne +2bcd : d0fe > bne * ;failed not equal (non zero) + > + +2bcf : b50c lda zpt,x +2bd1 : e8 inx +2bd2 : e002 cpx #2 +2bd4 : d002 bne tinc5 +2bd6 : a9fe lda #$fe +2bd8 : e005 tinc5 cpx #5 +2bda : d0db bne tinc4 +2bdc : ca dex +2bdd : a902 lda #2 +2bdf : 950c tdec4 sta zpt,x + set_stat 0 + > load_flag 0 +2be1 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2be3 : 48 > pha ;use stack to load status +2be4 : 28 > plp + +2be5 : d60c dec zpt,x + tst_zx rINC,fINC,0 +2be7 : 08 > php ;save flags +2be8 : b50c > lda zpt,x +2bea : dd4002 > cmp rINC,x ;test result + > trap_ne +2bed : d0fe > bne * ;failed not equal (non zero) + > +2bef : 68 > pla ;load status + > eor_flag 0 +2bf0 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2bf2 : dd4502 > cmp fINC,x ;test flags + > trap_ne +2bf5 : d0fe > bne * ;failed not equal (non zero) + > + +2bf7 : b50c lda zpt,x +2bf9 : ca dex +2bfa : 3008 bmi tdec5 +2bfc : e001 cpx #1 +2bfe : d0df bne tdec4 +2c00 : a981 lda #$81 +2c02 : d0db bne tdec4 +2c04 : tdec5 +2c04 : a200 ldx #0 +2c06 : a97e lda #$7e +2c08 : 950c tinc14 sta zpt,x + set_stat $ff + > load_flag $ff +2c0a : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2c0c : 48 > pha ;use stack to load status +2c0d : 28 > plp + +2c0e : f60c inc zpt,x + tst_zx rINC,fINC,$ff-fnz +2c10 : 08 > php ;save flags +2c11 : b50c > lda zpt,x +2c13 : dd4002 > cmp rINC,x ;test result + > trap_ne +2c16 : d0fe > bne * ;failed not equal (non zero) + > +2c18 : 68 > pla ;load status + > eor_flag $ff-fnz +2c19 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +2c1b : dd4502 > cmp fINC,x ;test flags + > trap_ne +2c1e : d0fe > bne * ;failed not equal (non zero) + > + +2c20 : b50c lda zpt,x +2c22 : e8 inx +2c23 : e002 cpx #2 +2c25 : d002 bne tinc15 +2c27 : a9fe lda #$fe +2c29 : e005 tinc15 cpx #5 +2c2b : d0db bne tinc14 +2c2d : ca dex +2c2e : a902 lda #2 +2c30 : 950c tdec14 sta zpt,x + set_stat $ff + > load_flag $ff +2c32 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2c34 : 48 > pha ;use stack to load status +2c35 : 28 > plp + +2c36 : d60c dec zpt,x + tst_zx rINC,fINC,$ff-fnz +2c38 : 08 > php ;save flags +2c39 : b50c > lda zpt,x +2c3b : dd4002 > cmp rINC,x ;test result + > trap_ne +2c3e : d0fe > bne * ;failed not equal (non zero) + > +2c40 : 68 > pla ;load status + > eor_flag $ff-fnz +2c41 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +2c43 : dd4502 > cmp fINC,x ;test flags + > trap_ne +2c46 : d0fe > bne * ;failed not equal (non zero) + > + +2c48 : b50c lda zpt,x +2c4a : ca dex +2c4b : 3008 bmi tdec15 +2c4d : e001 cpx #1 +2c4f : d0df bne tdec14 +2c51 : a981 lda #$81 +2c53 : d0db bne tdec14 +2c55 : tdec15 + next_test +2c55 : ad0002 > lda test_case ;previous test +2c58 : c924 > cmp #test_num + > trap_ne ;test is out of sequence +2c5a : d0fe > bne * ;failed not equal (non zero) + > +0025 = >test_num = test_num + 1 +2c5c : a925 > lda #test_num ;*** next tests' number +2c5e : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; memory indexed +2c61 : a200 ldx #0 +2c63 : a97e lda #$7e +2c65 : 9d0302 tinc6 sta abst,x + set_stat 0 + > load_flag 0 +2c68 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2c6a : 48 > pha ;use stack to load status +2c6b : 28 > plp + +2c6c : fe0302 inc abst,x + tst_absx rINC,fINC,0 +2c6f : 08 > php ;save flags +2c70 : bd0302 > lda abst,x +2c73 : dd4002 > cmp rINC,x ;test result + > trap_ne +2c76 : d0fe > bne * ;failed not equal (non zero) + > +2c78 : 68 > pla ;load status + > eor_flag 0 +2c79 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2c7b : dd4502 > cmp fINC,x ;test flags + > trap_ne +2c7e : d0fe > bne * ;failed not equal (non zero) + > + +2c80 : bd0302 lda abst,x +2c83 : e8 inx +2c84 : e002 cpx #2 +2c86 : d002 bne tinc7 +2c88 : a9fe lda #$fe +2c8a : e005 tinc7 cpx #5 +2c8c : d0d7 bne tinc6 +2c8e : ca dex +2c8f : a902 lda #2 +2c91 : 9d0302 tdec6 sta abst,x + set_stat 0 + > load_flag 0 +2c94 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2c96 : 48 > pha ;use stack to load status +2c97 : 28 > plp + +2c98 : de0302 dec abst,x + tst_absx rINC,fINC,0 +2c9b : 08 > php ;save flags +2c9c : bd0302 > lda abst,x +2c9f : dd4002 > cmp rINC,x ;test result + > trap_ne +2ca2 : d0fe > bne * ;failed not equal (non zero) + > +2ca4 : 68 > pla ;load status + > eor_flag 0 +2ca5 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2ca7 : dd4502 > cmp fINC,x ;test flags + > trap_ne +2caa : d0fe > bne * ;failed not equal (non zero) + > + +2cac : bd0302 lda abst,x +2caf : ca dex +2cb0 : 3008 bmi tdec7 +2cb2 : e001 cpx #1 +2cb4 : d0db bne tdec6 +2cb6 : a981 lda #$81 +2cb8 : d0d7 bne tdec6 +2cba : tdec7 +2cba : a200 ldx #0 +2cbc : a97e lda #$7e +2cbe : 9d0302 tinc16 sta abst,x + set_stat $ff + > load_flag $ff +2cc1 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2cc3 : 48 > pha ;use stack to load status +2cc4 : 28 > plp + +2cc5 : fe0302 inc abst,x + tst_absx rINC,fINC,$ff-fnz +2cc8 : 08 > php ;save flags +2cc9 : bd0302 > lda abst,x +2ccc : dd4002 > cmp rINC,x ;test result + > trap_ne +2ccf : d0fe > bne * ;failed not equal (non zero) + > +2cd1 : 68 > pla ;load status + > eor_flag $ff-fnz +2cd2 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +2cd4 : dd4502 > cmp fINC,x ;test flags + > trap_ne +2cd7 : d0fe > bne * ;failed not equal (non zero) + > + +2cd9 : bd0302 lda abst,x +2cdc : e8 inx +2cdd : e002 cpx #2 +2cdf : d002 bne tinc17 +2ce1 : a9fe lda #$fe +2ce3 : e005 tinc17 cpx #5 +2ce5 : d0d7 bne tinc16 +2ce7 : ca dex +2ce8 : a902 lda #2 +2cea : 9d0302 tdec16 sta abst,x + set_stat $ff + > load_flag $ff +2ced : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2cef : 48 > pha ;use stack to load status +2cf0 : 28 > plp + +2cf1 : de0302 dec abst,x + tst_absx rINC,fINC,$ff-fnz +2cf4 : 08 > php ;save flags +2cf5 : bd0302 > lda abst,x +2cf8 : dd4002 > cmp rINC,x ;test result + > trap_ne +2cfb : d0fe > bne * ;failed not equal (non zero) + > +2cfd : 68 > pla ;load status + > eor_flag $ff-fnz +2cfe : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +2d00 : dd4502 > cmp fINC,x ;test flags + > trap_ne +2d03 : d0fe > bne * ;failed not equal (non zero) + > + +2d05 : bd0302 lda abst,x +2d08 : ca dex +2d09 : 3008 bmi tdec17 +2d0b : e001 cpx #1 +2d0d : d0db bne tdec16 +2d0f : a981 lda #$81 +2d11 : d0d7 bne tdec16 +2d13 : tdec17 + next_test +2d13 : ad0002 > lda test_case ;previous test +2d16 : c925 > cmp #test_num + > trap_ne ;test is out of sequence +2d18 : d0fe > bne * ;failed not equal (non zero) + > +0026 = >test_num = test_num + 1 +2d1a : a926 > lda #test_num ;*** next tests' number +2d1c : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; testing logical instructions - AND EOR ORA all addressing modes + ; AND +2d1f : a203 ldx #3 ;immediate +2d21 : b51c tand lda zpAN,x +2d23 : 8d0902 sta ex_andi+1 ;set AND # operand + set_ax absANa,0 + > load_flag 0 +2d26 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2d28 : 48 > pha ;use stack to load status +2d29 : bd5a02 > lda absANa,x ;precharge accu +2d2c : 28 > plp + +2d2d : 200802 jsr ex_andi ;execute AND # in RAM + tst_ax absrlo,absflo,0 +2d30 : 08 > php ;save flags +2d31 : dd6202 > cmp absrlo,x ;test result + > trap_ne +2d34 : d0fe > bne * ;failed not equal (non zero) + > +2d36 : 68 > pla ;load status + > eor_flag 0 +2d37 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2d39 : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +2d3c : d0fe > bne * ;failed not equal (non zero) + > + +2d3e : ca dex +2d3f : 10e0 bpl tand +2d41 : a203 ldx #3 +2d43 : b51c tand1 lda zpAN,x +2d45 : 8d0902 sta ex_andi+1 ;set AND # operand + set_ax absANa,$ff + > load_flag $ff +2d48 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2d4a : 48 > pha ;use stack to load status +2d4b : bd5a02 > lda absANa,x ;precharge accu +2d4e : 28 > plp + +2d4f : 200802 jsr ex_andi ;execute AND # in RAM + tst_ax absrlo,absflo,$ff-fnz +2d52 : 08 > php ;save flags +2d53 : dd6202 > cmp absrlo,x ;test result + > trap_ne +2d56 : d0fe > bne * ;failed not equal (non zero) + > +2d58 : 68 > pla ;load status + > eor_flag $ff-fnz +2d59 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +2d5b : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +2d5e : d0fe > bne * ;failed not equal (non zero) + > + +2d60 : ca dex +2d61 : 10e0 bpl tand1 + +2d63 : a203 ldx #3 ;zp +2d65 : b51c tand2 lda zpAN,x +2d67 : 850c sta zpt + set_ax absANa,0 + > load_flag 0 +2d69 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2d6b : 48 > pha ;use stack to load status +2d6c : bd5a02 > lda absANa,x ;precharge accu +2d6f : 28 > plp + +2d70 : 250c and zpt + tst_ax absrlo,absflo,0 +2d72 : 08 > php ;save flags +2d73 : dd6202 > cmp absrlo,x ;test result + > trap_ne +2d76 : d0fe > bne * ;failed not equal (non zero) + > +2d78 : 68 > pla ;load status + > eor_flag 0 +2d79 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2d7b : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +2d7e : d0fe > bne * ;failed not equal (non zero) + > + +2d80 : ca dex +2d81 : 10e2 bpl tand2 +2d83 : a203 ldx #3 +2d85 : b51c tand3 lda zpAN,x +2d87 : 850c sta zpt + set_ax absANa,$ff + > load_flag $ff +2d89 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2d8b : 48 > pha ;use stack to load status +2d8c : bd5a02 > lda absANa,x ;precharge accu +2d8f : 28 > plp + +2d90 : 250c and zpt + tst_ax absrlo,absflo,$ff-fnz +2d92 : 08 > php ;save flags +2d93 : dd6202 > cmp absrlo,x ;test result + > trap_ne +2d96 : d0fe > bne * ;failed not equal (non zero) + > +2d98 : 68 > pla ;load status + > eor_flag $ff-fnz +2d99 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +2d9b : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +2d9e : d0fe > bne * ;failed not equal (non zero) + > + +2da0 : ca dex +2da1 : 10e2 bpl tand3 + +2da3 : a203 ldx #3 ;abs +2da5 : b51c tand4 lda zpAN,x +2da7 : 8d0302 sta abst + set_ax absANa,0 + > load_flag 0 +2daa : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2dac : 48 > pha ;use stack to load status +2dad : bd5a02 > lda absANa,x ;precharge accu +2db0 : 28 > plp + +2db1 : 2d0302 and abst + tst_ax absrlo,absflo,0 +2db4 : 08 > php ;save flags +2db5 : dd6202 > cmp absrlo,x ;test result + > trap_ne +2db8 : d0fe > bne * ;failed not equal (non zero) + > +2dba : 68 > pla ;load status + > eor_flag 0 +2dbb : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2dbd : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +2dc0 : d0fe > bne * ;failed not equal (non zero) + > + +2dc2 : ca dex +2dc3 : 10e0 bpl tand4 +2dc5 : a203 ldx #3 +2dc7 : b51c tand5 lda zpAN,x +2dc9 : 8d0302 sta abst + set_ax absANa,$ff + > load_flag $ff +2dcc : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2dce : 48 > pha ;use stack to load status +2dcf : bd5a02 > lda absANa,x ;precharge accu +2dd2 : 28 > plp + +2dd3 : 2d0302 and abst + tst_ax absrlo,absflo,$ff-fnz +2dd6 : 08 > php ;save flags +2dd7 : dd6202 > cmp absrlo,x ;test result + > trap_ne +2dda : d0fe > bne * ;failed not equal (non zero) + > +2ddc : 68 > pla ;load status + > eor_flag $ff-fnz +2ddd : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +2ddf : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +2de2 : d0fe > bne * ;failed not equal (non zero) + > + +2de4 : ca dex +2de5 : 1002 bpl tand6 + +2de7 : a203 ldx #3 ;zp,x +2de9 : tand6 + set_ax absANa,0 + > load_flag 0 +2de9 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2deb : 48 > pha ;use stack to load status +2dec : bd5a02 > lda absANa,x ;precharge accu +2def : 28 > plp + +2df0 : 351c and zpAN,x + tst_ax absrlo,absflo,0 +2df2 : 08 > php ;save flags +2df3 : dd6202 > cmp absrlo,x ;test result + > trap_ne +2df6 : d0fe > bne * ;failed not equal (non zero) + > +2df8 : 68 > pla ;load status + > eor_flag 0 +2df9 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2dfb : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +2dfe : d0fe > bne * ;failed not equal (non zero) + > + +2e00 : ca dex +2e01 : 10e6 bpl tand6 +2e03 : a203 ldx #3 +2e05 : tand7 + set_ax absANa,$ff + > load_flag $ff +2e05 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2e07 : 48 > pha ;use stack to load status +2e08 : bd5a02 > lda absANa,x ;precharge accu +2e0b : 28 > plp + +2e0c : 351c and zpAN,x + tst_ax absrlo,absflo,$ff-fnz +2e0e : 08 > php ;save flags +2e0f : dd6202 > cmp absrlo,x ;test result + > trap_ne +2e12 : d0fe > bne * ;failed not equal (non zero) + > +2e14 : 68 > pla ;load status + > eor_flag $ff-fnz +2e15 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +2e17 : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +2e1a : d0fe > bne * ;failed not equal (non zero) + > + +2e1c : ca dex +2e1d : 10e6 bpl tand7 + +2e1f : a203 ldx #3 ;abs,x +2e21 : tand8 + set_ax absANa,0 + > load_flag 0 +2e21 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2e23 : 48 > pha ;use stack to load status +2e24 : bd5a02 > lda absANa,x ;precharge accu +2e27 : 28 > plp + +2e28 : 3d4e02 and absAN,x + tst_ax absrlo,absflo,0 +2e2b : 08 > php ;save flags +2e2c : dd6202 > cmp absrlo,x ;test result + > trap_ne +2e2f : d0fe > bne * ;failed not equal (non zero) + > +2e31 : 68 > pla ;load status + > eor_flag 0 +2e32 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2e34 : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +2e37 : d0fe > bne * ;failed not equal (non zero) + > + +2e39 : ca dex +2e3a : 10e5 bpl tand8 +2e3c : a203 ldx #3 +2e3e : tand9 + set_ax absANa,$ff + > load_flag $ff +2e3e : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2e40 : 48 > pha ;use stack to load status +2e41 : bd5a02 > lda absANa,x ;precharge accu +2e44 : 28 > plp + +2e45 : 3d4e02 and absAN,x + tst_ax absrlo,absflo,$ff-fnz +2e48 : 08 > php ;save flags +2e49 : dd6202 > cmp absrlo,x ;test result + > trap_ne +2e4c : d0fe > bne * ;failed not equal (non zero) + > +2e4e : 68 > pla ;load status + > eor_flag $ff-fnz +2e4f : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +2e51 : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +2e54 : d0fe > bne * ;failed not equal (non zero) + > + +2e56 : ca dex +2e57 : 10e5 bpl tand9 + +2e59 : a003 ldy #3 ;abs,y +2e5b : tand10 + set_ay absANa,0 + > load_flag 0 +2e5b : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2e5d : 48 > pha ;use stack to load status +2e5e : b95a02 > lda absANa,y ;precharge accu +2e61 : 28 > plp + +2e62 : 394e02 and absAN,y + tst_ay absrlo,absflo,0 +2e65 : 08 > php ;save flags +2e66 : d96202 > cmp absrlo,y ;test result + > trap_ne ; +2e69 : d0fe > bne * ;failed not equal (non zero) + > +2e6b : 68 > pla ;load status + > eor_flag 0 +2e6c : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2e6e : d96602 > cmp absflo,y ;test flags + > trap_ne +2e71 : d0fe > bne * ;failed not equal (non zero) + > + +2e73 : 88 dey +2e74 : 10e5 bpl tand10 +2e76 : a003 ldy #3 +2e78 : tand11 + set_ay absANa,$ff + > load_flag $ff +2e78 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2e7a : 48 > pha ;use stack to load status +2e7b : b95a02 > lda absANa,y ;precharge accu +2e7e : 28 > plp + +2e7f : 394e02 and absAN,y + tst_ay absrlo,absflo,$ff-fnz +2e82 : 08 > php ;save flags +2e83 : d96202 > cmp absrlo,y ;test result + > trap_ne ; +2e86 : d0fe > bne * ;failed not equal (non zero) + > +2e88 : 68 > pla ;load status + > eor_flag $ff-fnz +2e89 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +2e8b : d96602 > cmp absflo,y ;test flags + > trap_ne +2e8e : d0fe > bne * ;failed not equal (non zero) + > + +2e90 : 88 dey +2e91 : 10e5 bpl tand11 + +2e93 : a206 ldx #6 ;(zp,x) +2e95 : a003 ldy #3 +2e97 : tand12 + set_ay absANa,0 + > load_flag 0 +2e97 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2e99 : 48 > pha ;use stack to load status +2e9a : b95a02 > lda absANa,y ;precharge accu +2e9d : 28 > plp + +2e9e : 213a and (indAN,x) + tst_ay absrlo,absflo,0 +2ea0 : 08 > php ;save flags +2ea1 : d96202 > cmp absrlo,y ;test result + > trap_ne ; +2ea4 : d0fe > bne * ;failed not equal (non zero) + > +2ea6 : 68 > pla ;load status + > eor_flag 0 +2ea7 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2ea9 : d96602 > cmp absflo,y ;test flags + > trap_ne +2eac : d0fe > bne * ;failed not equal (non zero) + > + +2eae : ca dex +2eaf : ca dex +2eb0 : 88 dey +2eb1 : 10e4 bpl tand12 +2eb3 : a206 ldx #6 +2eb5 : a003 ldy #3 +2eb7 : tand13 + set_ay absANa,$ff + > load_flag $ff +2eb7 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2eb9 : 48 > pha ;use stack to load status +2eba : b95a02 > lda absANa,y ;precharge accu +2ebd : 28 > plp + +2ebe : 213a and (indAN,x) + tst_ay absrlo,absflo,$ff-fnz +2ec0 : 08 > php ;save flags +2ec1 : d96202 > cmp absrlo,y ;test result + > trap_ne ; +2ec4 : d0fe > bne * ;failed not equal (non zero) + > +2ec6 : 68 > pla ;load status + > eor_flag $ff-fnz +2ec7 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +2ec9 : d96602 > cmp absflo,y ;test flags + > trap_ne +2ecc : d0fe > bne * ;failed not equal (non zero) + > + +2ece : ca dex +2ecf : ca dex +2ed0 : 88 dey +2ed1 : 10e4 bpl tand13 + +2ed3 : a003 ldy #3 ;(zp),y +2ed5 : tand14 + set_ay absANa,0 + > load_flag 0 +2ed5 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2ed7 : 48 > pha ;use stack to load status +2ed8 : b95a02 > lda absANa,y ;precharge accu +2edb : 28 > plp + +2edc : 313a and (indAN),y + tst_ay absrlo,absflo,0 +2ede : 08 > php ;save flags +2edf : d96202 > cmp absrlo,y ;test result + > trap_ne ; +2ee2 : d0fe > bne * ;failed not equal (non zero) + > +2ee4 : 68 > pla ;load status + > eor_flag 0 +2ee5 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2ee7 : d96602 > cmp absflo,y ;test flags + > trap_ne +2eea : d0fe > bne * ;failed not equal (non zero) + > + +2eec : 88 dey +2eed : 10e6 bpl tand14 +2eef : a003 ldy #3 +2ef1 : tand15 + set_ay absANa,$ff + > load_flag $ff +2ef1 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2ef3 : 48 > pha ;use stack to load status +2ef4 : b95a02 > lda absANa,y ;precharge accu +2ef7 : 28 > plp + +2ef8 : 313a and (indAN),y + tst_ay absrlo,absflo,$ff-fnz +2efa : 08 > php ;save flags +2efb : d96202 > cmp absrlo,y ;test result + > trap_ne ; +2efe : d0fe > bne * ;failed not equal (non zero) + > +2f00 : 68 > pla ;load status + > eor_flag $ff-fnz +2f01 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +2f03 : d96602 > cmp absflo,y ;test flags + > trap_ne +2f06 : d0fe > bne * ;failed not equal (non zero) + > + +2f08 : 88 dey +2f09 : 10e6 bpl tand15 + next_test +2f0b : ad0002 > lda test_case ;previous test +2f0e : c926 > cmp #test_num + > trap_ne ;test is out of sequence +2f10 : d0fe > bne * ;failed not equal (non zero) + > +0027 = >test_num = test_num + 1 +2f12 : a927 > lda #test_num ;*** next tests' number +2f14 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; EOR +2f17 : a203 ldx #3 ;immediate - self modifying code +2f19 : b520 teor lda zpEO,x +2f1b : 8d0c02 sta ex_eori+1 ;set EOR # operand + set_ax absEOa,0 + > load_flag 0 +2f1e : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2f20 : 48 > pha ;use stack to load status +2f21 : bd5e02 > lda absEOa,x ;precharge accu +2f24 : 28 > plp + +2f25 : 200b02 jsr ex_eori ;execute EOR # in RAM + tst_ax absrlo,absflo,0 +2f28 : 08 > php ;save flags +2f29 : dd6202 > cmp absrlo,x ;test result + > trap_ne +2f2c : d0fe > bne * ;failed not equal (non zero) + > +2f2e : 68 > pla ;load status + > eor_flag 0 +2f2f : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2f31 : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +2f34 : d0fe > bne * ;failed not equal (non zero) + > + +2f36 : ca dex +2f37 : 10e0 bpl teor +2f39 : a203 ldx #3 +2f3b : b520 teor1 lda zpEO,x +2f3d : 8d0c02 sta ex_eori+1 ;set EOR # operand + set_ax absEOa,$ff + > load_flag $ff +2f40 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2f42 : 48 > pha ;use stack to load status +2f43 : bd5e02 > lda absEOa,x ;precharge accu +2f46 : 28 > plp + +2f47 : 200b02 jsr ex_eori ;execute EOR # in RAM + tst_ax absrlo,absflo,$ff-fnz +2f4a : 08 > php ;save flags +2f4b : dd6202 > cmp absrlo,x ;test result + > trap_ne +2f4e : d0fe > bne * ;failed not equal (non zero) + > +2f50 : 68 > pla ;load status + > eor_flag $ff-fnz +2f51 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +2f53 : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +2f56 : d0fe > bne * ;failed not equal (non zero) + > + +2f58 : ca dex +2f59 : 10e0 bpl teor1 + +2f5b : a203 ldx #3 ;zp +2f5d : b520 teor2 lda zpEO,x +2f5f : 850c sta zpt + set_ax absEOa,0 + > load_flag 0 +2f61 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2f63 : 48 > pha ;use stack to load status +2f64 : bd5e02 > lda absEOa,x ;precharge accu +2f67 : 28 > plp + +2f68 : 450c eor zpt + tst_ax absrlo,absflo,0 +2f6a : 08 > php ;save flags +2f6b : dd6202 > cmp absrlo,x ;test result + > trap_ne +2f6e : d0fe > bne * ;failed not equal (non zero) + > +2f70 : 68 > pla ;load status + > eor_flag 0 +2f71 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2f73 : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +2f76 : d0fe > bne * ;failed not equal (non zero) + > + +2f78 : ca dex +2f79 : 10e2 bpl teor2 +2f7b : a203 ldx #3 +2f7d : b520 teor3 lda zpEO,x +2f7f : 850c sta zpt + set_ax absEOa,$ff + > load_flag $ff +2f81 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2f83 : 48 > pha ;use stack to load status +2f84 : bd5e02 > lda absEOa,x ;precharge accu +2f87 : 28 > plp + +2f88 : 450c eor zpt + tst_ax absrlo,absflo,$ff-fnz +2f8a : 08 > php ;save flags +2f8b : dd6202 > cmp absrlo,x ;test result + > trap_ne +2f8e : d0fe > bne * ;failed not equal (non zero) + > +2f90 : 68 > pla ;load status + > eor_flag $ff-fnz +2f91 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +2f93 : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +2f96 : d0fe > bne * ;failed not equal (non zero) + > + +2f98 : ca dex +2f99 : 10e2 bpl teor3 + +2f9b : a203 ldx #3 ;abs +2f9d : b520 teor4 lda zpEO,x +2f9f : 8d0302 sta abst + set_ax absEOa,0 + > load_flag 0 +2fa2 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2fa4 : 48 > pha ;use stack to load status +2fa5 : bd5e02 > lda absEOa,x ;precharge accu +2fa8 : 28 > plp + +2fa9 : 4d0302 eor abst + tst_ax absrlo,absflo,0 +2fac : 08 > php ;save flags +2fad : dd6202 > cmp absrlo,x ;test result + > trap_ne +2fb0 : d0fe > bne * ;failed not equal (non zero) + > +2fb2 : 68 > pla ;load status + > eor_flag 0 +2fb3 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2fb5 : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +2fb8 : d0fe > bne * ;failed not equal (non zero) + > + +2fba : ca dex +2fbb : 10e0 bpl teor4 +2fbd : a203 ldx #3 +2fbf : b520 teor5 lda zpEO,x +2fc1 : 8d0302 sta abst + set_ax absEOa,$ff + > load_flag $ff +2fc4 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2fc6 : 48 > pha ;use stack to load status +2fc7 : bd5e02 > lda absEOa,x ;precharge accu +2fca : 28 > plp + +2fcb : 4d0302 eor abst + tst_ax absrlo,absflo,$ff-fnz +2fce : 08 > php ;save flags +2fcf : dd6202 > cmp absrlo,x ;test result + > trap_ne +2fd2 : d0fe > bne * ;failed not equal (non zero) + > +2fd4 : 68 > pla ;load status + > eor_flag $ff-fnz +2fd5 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +2fd7 : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +2fda : d0fe > bne * ;failed not equal (non zero) + > + +2fdc : ca dex +2fdd : 1002 bpl teor6 + +2fdf : a203 ldx #3 ;zp,x +2fe1 : teor6 + set_ax absEOa,0 + > load_flag 0 +2fe1 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +2fe3 : 48 > pha ;use stack to load status +2fe4 : bd5e02 > lda absEOa,x ;precharge accu +2fe7 : 28 > plp + +2fe8 : 5520 eor zpEO,x + tst_ax absrlo,absflo,0 +2fea : 08 > php ;save flags +2feb : dd6202 > cmp absrlo,x ;test result + > trap_ne +2fee : d0fe > bne * ;failed not equal (non zero) + > +2ff0 : 68 > pla ;load status + > eor_flag 0 +2ff1 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +2ff3 : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +2ff6 : d0fe > bne * ;failed not equal (non zero) + > + +2ff8 : ca dex +2ff9 : 10e6 bpl teor6 +2ffb : a203 ldx #3 +2ffd : teor7 + set_ax absEOa,$ff + > load_flag $ff +2ffd : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +2fff : 48 > pha ;use stack to load status +3000 : bd5e02 > lda absEOa,x ;precharge accu +3003 : 28 > plp + +3004 : 5520 eor zpEO,x + tst_ax absrlo,absflo,$ff-fnz +3006 : 08 > php ;save flags +3007 : dd6202 > cmp absrlo,x ;test result + > trap_ne +300a : d0fe > bne * ;failed not equal (non zero) + > +300c : 68 > pla ;load status + > eor_flag $ff-fnz +300d : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +300f : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +3012 : d0fe > bne * ;failed not equal (non zero) + > + +3014 : ca dex +3015 : 10e6 bpl teor7 + +3017 : a203 ldx #3 ;abs,x +3019 : teor8 + set_ax absEOa,0 + > load_flag 0 +3019 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +301b : 48 > pha ;use stack to load status +301c : bd5e02 > lda absEOa,x ;precharge accu +301f : 28 > plp + +3020 : 5d5202 eor absEO,x + tst_ax absrlo,absflo,0 +3023 : 08 > php ;save flags +3024 : dd6202 > cmp absrlo,x ;test result + > trap_ne +3027 : d0fe > bne * ;failed not equal (non zero) + > +3029 : 68 > pla ;load status + > eor_flag 0 +302a : 4930 > eor #0|fao ;invert expected flags + always on bits + > +302c : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +302f : d0fe > bne * ;failed not equal (non zero) + > + +3031 : ca dex +3032 : 10e5 bpl teor8 +3034 : a203 ldx #3 +3036 : teor9 + set_ax absEOa,$ff + > load_flag $ff +3036 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +3038 : 48 > pha ;use stack to load status +3039 : bd5e02 > lda absEOa,x ;precharge accu +303c : 28 > plp + +303d : 5d5202 eor absEO,x + tst_ax absrlo,absflo,$ff-fnz +3040 : 08 > php ;save flags +3041 : dd6202 > cmp absrlo,x ;test result + > trap_ne +3044 : d0fe > bne * ;failed not equal (non zero) + > +3046 : 68 > pla ;load status + > eor_flag $ff-fnz +3047 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +3049 : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +304c : d0fe > bne * ;failed not equal (non zero) + > + +304e : ca dex +304f : 10e5 bpl teor9 + +3051 : a003 ldy #3 ;abs,y +3053 : teor10 + set_ay absEOa,0 + > load_flag 0 +3053 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +3055 : 48 > pha ;use stack to load status +3056 : b95e02 > lda absEOa,y ;precharge accu +3059 : 28 > plp + +305a : 595202 eor absEO,y + tst_ay absrlo,absflo,0 +305d : 08 > php ;save flags +305e : d96202 > cmp absrlo,y ;test result + > trap_ne ; +3061 : d0fe > bne * ;failed not equal (non zero) + > +3063 : 68 > pla ;load status + > eor_flag 0 +3064 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +3066 : d96602 > cmp absflo,y ;test flags + > trap_ne +3069 : d0fe > bne * ;failed not equal (non zero) + > + +306b : 88 dey +306c : 10e5 bpl teor10 +306e : a003 ldy #3 +3070 : teor11 + set_ay absEOa,$ff + > load_flag $ff +3070 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +3072 : 48 > pha ;use stack to load status +3073 : b95e02 > lda absEOa,y ;precharge accu +3076 : 28 > plp + +3077 : 595202 eor absEO,y + tst_ay absrlo,absflo,$ff-fnz +307a : 08 > php ;save flags +307b : d96202 > cmp absrlo,y ;test result + > trap_ne ; +307e : d0fe > bne * ;failed not equal (non zero) + > +3080 : 68 > pla ;load status + > eor_flag $ff-fnz +3081 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +3083 : d96602 > cmp absflo,y ;test flags + > trap_ne +3086 : d0fe > bne * ;failed not equal (non zero) + > + +3088 : 88 dey +3089 : 10e5 bpl teor11 + +308b : a206 ldx #6 ;(zp,x) +308d : a003 ldy #3 +308f : teor12 + set_ay absEOa,0 + > load_flag 0 +308f : a900 > lda #0 ;allow test to change I-flag (no mask) + > +3091 : 48 > pha ;use stack to load status +3092 : b95e02 > lda absEOa,y ;precharge accu +3095 : 28 > plp + +3096 : 4142 eor (indEO,x) + tst_ay absrlo,absflo,0 +3098 : 08 > php ;save flags +3099 : d96202 > cmp absrlo,y ;test result + > trap_ne ; +309c : d0fe > bne * ;failed not equal (non zero) + > +309e : 68 > pla ;load status + > eor_flag 0 +309f : 4930 > eor #0|fao ;invert expected flags + always on bits + > +30a1 : d96602 > cmp absflo,y ;test flags + > trap_ne +30a4 : d0fe > bne * ;failed not equal (non zero) + > + +30a6 : ca dex +30a7 : ca dex +30a8 : 88 dey +30a9 : 10e4 bpl teor12 +30ab : a206 ldx #6 +30ad : a003 ldy #3 +30af : teor13 + set_ay absEOa,$ff + > load_flag $ff +30af : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +30b1 : 48 > pha ;use stack to load status +30b2 : b95e02 > lda absEOa,y ;precharge accu +30b5 : 28 > plp + +30b6 : 4142 eor (indEO,x) + tst_ay absrlo,absflo,$ff-fnz +30b8 : 08 > php ;save flags +30b9 : d96202 > cmp absrlo,y ;test result + > trap_ne ; +30bc : d0fe > bne * ;failed not equal (non zero) + > +30be : 68 > pla ;load status + > eor_flag $ff-fnz +30bf : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +30c1 : d96602 > cmp absflo,y ;test flags + > trap_ne +30c4 : d0fe > bne * ;failed not equal (non zero) + > + +30c6 : ca dex +30c7 : ca dex +30c8 : 88 dey +30c9 : 10e4 bpl teor13 + +30cb : a003 ldy #3 ;(zp),y +30cd : teor14 + set_ay absEOa,0 + > load_flag 0 +30cd : a900 > lda #0 ;allow test to change I-flag (no mask) + > +30cf : 48 > pha ;use stack to load status +30d0 : b95e02 > lda absEOa,y ;precharge accu +30d3 : 28 > plp + +30d4 : 5142 eor (indEO),y + tst_ay absrlo,absflo,0 +30d6 : 08 > php ;save flags +30d7 : d96202 > cmp absrlo,y ;test result + > trap_ne ; +30da : d0fe > bne * ;failed not equal (non zero) + > +30dc : 68 > pla ;load status + > eor_flag 0 +30dd : 4930 > eor #0|fao ;invert expected flags + always on bits + > +30df : d96602 > cmp absflo,y ;test flags + > trap_ne +30e2 : d0fe > bne * ;failed not equal (non zero) + > + +30e4 : 88 dey +30e5 : 10e6 bpl teor14 +30e7 : a003 ldy #3 +30e9 : teor15 + set_ay absEOa,$ff + > load_flag $ff +30e9 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +30eb : 48 > pha ;use stack to load status +30ec : b95e02 > lda absEOa,y ;precharge accu +30ef : 28 > plp + +30f0 : 5142 eor (indEO),y + tst_ay absrlo,absflo,$ff-fnz +30f2 : 08 > php ;save flags +30f3 : d96202 > cmp absrlo,y ;test result + > trap_ne ; +30f6 : d0fe > bne * ;failed not equal (non zero) + > +30f8 : 68 > pla ;load status + > eor_flag $ff-fnz +30f9 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +30fb : d96602 > cmp absflo,y ;test flags + > trap_ne +30fe : d0fe > bne * ;failed not equal (non zero) + > + +3100 : 88 dey +3101 : 10e6 bpl teor15 + next_test +3103 : ad0002 > lda test_case ;previous test +3106 : c927 > cmp #test_num + > trap_ne ;test is out of sequence +3108 : d0fe > bne * ;failed not equal (non zero) + > +0028 = >test_num = test_num + 1 +310a : a928 > lda #test_num ;*** next tests' number +310c : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; OR +310f : a203 ldx #3 ;immediate - self modifying code +3111 : b518 tora lda zpOR,x +3113 : 8d0f02 sta ex_orai+1 ;set ORA # operand + set_ax absORa,0 + > load_flag 0 +3116 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +3118 : 48 > pha ;use stack to load status +3119 : bd5602 > lda absORa,x ;precharge accu +311c : 28 > plp + +311d : 200e02 jsr ex_orai ;execute ORA # in RAM + tst_ax absrlo,absflo,0 +3120 : 08 > php ;save flags +3121 : dd6202 > cmp absrlo,x ;test result + > trap_ne +3124 : d0fe > bne * ;failed not equal (non zero) + > +3126 : 68 > pla ;load status + > eor_flag 0 +3127 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +3129 : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +312c : d0fe > bne * ;failed not equal (non zero) + > + +312e : ca dex +312f : 10e0 bpl tora +3131 : a203 ldx #3 +3133 : b518 tora1 lda zpOR,x +3135 : 8d0f02 sta ex_orai+1 ;set ORA # operand + set_ax absORa,$ff + > load_flag $ff +3138 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +313a : 48 > pha ;use stack to load status +313b : bd5602 > lda absORa,x ;precharge accu +313e : 28 > plp + +313f : 200e02 jsr ex_orai ;execute ORA # in RAM + tst_ax absrlo,absflo,$ff-fnz +3142 : 08 > php ;save flags +3143 : dd6202 > cmp absrlo,x ;test result + > trap_ne +3146 : d0fe > bne * ;failed not equal (non zero) + > +3148 : 68 > pla ;load status + > eor_flag $ff-fnz +3149 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +314b : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +314e : d0fe > bne * ;failed not equal (non zero) + > + +3150 : ca dex +3151 : 10e0 bpl tora1 + +3153 : a203 ldx #3 ;zp +3155 : b518 tora2 lda zpOR,x +3157 : 850c sta zpt + set_ax absORa,0 + > load_flag 0 +3159 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +315b : 48 > pha ;use stack to load status +315c : bd5602 > lda absORa,x ;precharge accu +315f : 28 > plp + +3160 : 050c ora zpt + tst_ax absrlo,absflo,0 +3162 : 08 > php ;save flags +3163 : dd6202 > cmp absrlo,x ;test result + > trap_ne +3166 : d0fe > bne * ;failed not equal (non zero) + > +3168 : 68 > pla ;load status + > eor_flag 0 +3169 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +316b : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +316e : d0fe > bne * ;failed not equal (non zero) + > + +3170 : ca dex +3171 : 10e2 bpl tora2 +3173 : a203 ldx #3 +3175 : b518 tora3 lda zpOR,x +3177 : 850c sta zpt + set_ax absORa,$ff + > load_flag $ff +3179 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +317b : 48 > pha ;use stack to load status +317c : bd5602 > lda absORa,x ;precharge accu +317f : 28 > plp + +3180 : 050c ora zpt + tst_ax absrlo,absflo,$ff-fnz +3182 : 08 > php ;save flags +3183 : dd6202 > cmp absrlo,x ;test result + > trap_ne +3186 : d0fe > bne * ;failed not equal (non zero) + > +3188 : 68 > pla ;load status + > eor_flag $ff-fnz +3189 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +318b : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +318e : d0fe > bne * ;failed not equal (non zero) + > + +3190 : ca dex +3191 : 10e2 bpl tora3 + +3193 : a203 ldx #3 ;abs +3195 : b518 tora4 lda zpOR,x +3197 : 8d0302 sta abst + set_ax absORa,0 + > load_flag 0 +319a : a900 > lda #0 ;allow test to change I-flag (no mask) + > +319c : 48 > pha ;use stack to load status +319d : bd5602 > lda absORa,x ;precharge accu +31a0 : 28 > plp + +31a1 : 0d0302 ora abst + tst_ax absrlo,absflo,0 +31a4 : 08 > php ;save flags +31a5 : dd6202 > cmp absrlo,x ;test result + > trap_ne +31a8 : d0fe > bne * ;failed not equal (non zero) + > +31aa : 68 > pla ;load status + > eor_flag 0 +31ab : 4930 > eor #0|fao ;invert expected flags + always on bits + > +31ad : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +31b0 : d0fe > bne * ;failed not equal (non zero) + > + +31b2 : ca dex +31b3 : 10e0 bpl tora4 +31b5 : a203 ldx #3 +31b7 : b518 tora5 lda zpOR,x +31b9 : 8d0302 sta abst + set_ax absORa,$ff + > load_flag $ff +31bc : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +31be : 48 > pha ;use stack to load status +31bf : bd5602 > lda absORa,x ;precharge accu +31c2 : 28 > plp + +31c3 : 0d0302 ora abst + tst_ax absrlo,absflo,$ff-fnz +31c6 : 08 > php ;save flags +31c7 : dd6202 > cmp absrlo,x ;test result + > trap_ne +31ca : d0fe > bne * ;failed not equal (non zero) + > +31cc : 68 > pla ;load status + > eor_flag $ff-fnz +31cd : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +31cf : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +31d2 : d0fe > bne * ;failed not equal (non zero) + > + +31d4 : ca dex +31d5 : 1002 bpl tora6 + +31d7 : a203 ldx #3 ;zp,x +31d9 : tora6 + set_ax absORa,0 + > load_flag 0 +31d9 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +31db : 48 > pha ;use stack to load status +31dc : bd5602 > lda absORa,x ;precharge accu +31df : 28 > plp + +31e0 : 1518 ora zpOR,x + tst_ax absrlo,absflo,0 +31e2 : 08 > php ;save flags +31e3 : dd6202 > cmp absrlo,x ;test result + > trap_ne +31e6 : d0fe > bne * ;failed not equal (non zero) + > +31e8 : 68 > pla ;load status + > eor_flag 0 +31e9 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +31eb : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +31ee : d0fe > bne * ;failed not equal (non zero) + > + +31f0 : ca dex +31f1 : 10e6 bpl tora6 +31f3 : a203 ldx #3 +31f5 : tora7 + set_ax absORa,$ff + > load_flag $ff +31f5 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +31f7 : 48 > pha ;use stack to load status +31f8 : bd5602 > lda absORa,x ;precharge accu +31fb : 28 > plp + +31fc : 1518 ora zpOR,x + tst_ax absrlo,absflo,$ff-fnz +31fe : 08 > php ;save flags +31ff : dd6202 > cmp absrlo,x ;test result + > trap_ne +3202 : d0fe > bne * ;failed not equal (non zero) + > +3204 : 68 > pla ;load status + > eor_flag $ff-fnz +3205 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +3207 : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +320a : d0fe > bne * ;failed not equal (non zero) + > + +320c : ca dex +320d : 10e6 bpl tora7 + +320f : a203 ldx #3 ;abs,x +3211 : tora8 + set_ax absORa,0 + > load_flag 0 +3211 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +3213 : 48 > pha ;use stack to load status +3214 : bd5602 > lda absORa,x ;precharge accu +3217 : 28 > plp + +3218 : 1d4a02 ora absOR,x + tst_ax absrlo,absflo,0 +321b : 08 > php ;save flags +321c : dd6202 > cmp absrlo,x ;test result + > trap_ne +321f : d0fe > bne * ;failed not equal (non zero) + > +3221 : 68 > pla ;load status + > eor_flag 0 +3222 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +3224 : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +3227 : d0fe > bne * ;failed not equal (non zero) + > + +3229 : ca dex +322a : 10e5 bpl tora8 +322c : a203 ldx #3 +322e : tora9 + set_ax absORa,$ff + > load_flag $ff +322e : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +3230 : 48 > pha ;use stack to load status +3231 : bd5602 > lda absORa,x ;precharge accu +3234 : 28 > plp + +3235 : 1d4a02 ora absOR,x + tst_ax absrlo,absflo,$ff-fnz +3238 : 08 > php ;save flags +3239 : dd6202 > cmp absrlo,x ;test result + > trap_ne +323c : d0fe > bne * ;failed not equal (non zero) + > +323e : 68 > pla ;load status + > eor_flag $ff-fnz +323f : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +3241 : dd6602 > cmp absflo,x ;test flags + > trap_ne ; +3244 : d0fe > bne * ;failed not equal (non zero) + > + +3246 : ca dex +3247 : 10e5 bpl tora9 + +3249 : a003 ldy #3 ;abs,y +324b : tora10 + set_ay absORa,0 + > load_flag 0 +324b : a900 > lda #0 ;allow test to change I-flag (no mask) + > +324d : 48 > pha ;use stack to load status +324e : b95602 > lda absORa,y ;precharge accu +3251 : 28 > plp + +3252 : 194a02 ora absOR,y + tst_ay absrlo,absflo,0 +3255 : 08 > php ;save flags +3256 : d96202 > cmp absrlo,y ;test result + > trap_ne ; +3259 : d0fe > bne * ;failed not equal (non zero) + > +325b : 68 > pla ;load status + > eor_flag 0 +325c : 4930 > eor #0|fao ;invert expected flags + always on bits + > +325e : d96602 > cmp absflo,y ;test flags + > trap_ne +3261 : d0fe > bne * ;failed not equal (non zero) + > + +3263 : 88 dey +3264 : 10e5 bpl tora10 +3266 : a003 ldy #3 +3268 : tora11 + set_ay absORa,$ff + > load_flag $ff +3268 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +326a : 48 > pha ;use stack to load status +326b : b95602 > lda absORa,y ;precharge accu +326e : 28 > plp + +326f : 194a02 ora absOR,y + tst_ay absrlo,absflo,$ff-fnz +3272 : 08 > php ;save flags +3273 : d96202 > cmp absrlo,y ;test result + > trap_ne ; +3276 : d0fe > bne * ;failed not equal (non zero) + > +3278 : 68 > pla ;load status + > eor_flag $ff-fnz +3279 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +327b : d96602 > cmp absflo,y ;test flags + > trap_ne +327e : d0fe > bne * ;failed not equal (non zero) + > + +3280 : 88 dey +3281 : 10e5 bpl tora11 + +3283 : a206 ldx #6 ;(zp,x) +3285 : a003 ldy #3 +3287 : tora12 + set_ay absORa,0 + > load_flag 0 +3287 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +3289 : 48 > pha ;use stack to load status +328a : b95602 > lda absORa,y ;precharge accu +328d : 28 > plp + +328e : 014a ora (indOR,x) + tst_ay absrlo,absflo,0 +3290 : 08 > php ;save flags +3291 : d96202 > cmp absrlo,y ;test result + > trap_ne ; +3294 : d0fe > bne * ;failed not equal (non zero) + > +3296 : 68 > pla ;load status + > eor_flag 0 +3297 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +3299 : d96602 > cmp absflo,y ;test flags + > trap_ne +329c : d0fe > bne * ;failed not equal (non zero) + > + +329e : ca dex +329f : ca dex +32a0 : 88 dey +32a1 : 10e4 bpl tora12 +32a3 : a206 ldx #6 +32a5 : a003 ldy #3 +32a7 : tora13 + set_ay absORa,$ff + > load_flag $ff +32a7 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +32a9 : 48 > pha ;use stack to load status +32aa : b95602 > lda absORa,y ;precharge accu +32ad : 28 > plp + +32ae : 014a ora (indOR,x) + tst_ay absrlo,absflo,$ff-fnz +32b0 : 08 > php ;save flags +32b1 : d96202 > cmp absrlo,y ;test result + > trap_ne ; +32b4 : d0fe > bne * ;failed not equal (non zero) + > +32b6 : 68 > pla ;load status + > eor_flag $ff-fnz +32b7 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +32b9 : d96602 > cmp absflo,y ;test flags + > trap_ne +32bc : d0fe > bne * ;failed not equal (non zero) + > + +32be : ca dex +32bf : ca dex +32c0 : 88 dey +32c1 : 10e4 bpl tora13 + +32c3 : a003 ldy #3 ;(zp),y +32c5 : tora14 + set_ay absORa,0 + > load_flag 0 +32c5 : a900 > lda #0 ;allow test to change I-flag (no mask) + > +32c7 : 48 > pha ;use stack to load status +32c8 : b95602 > lda absORa,y ;precharge accu +32cb : 28 > plp + +32cc : 114a ora (indOR),y + tst_ay absrlo,absflo,0 +32ce : 08 > php ;save flags +32cf : d96202 > cmp absrlo,y ;test result + > trap_ne ; +32d2 : d0fe > bne * ;failed not equal (non zero) + > +32d4 : 68 > pla ;load status + > eor_flag 0 +32d5 : 4930 > eor #0|fao ;invert expected flags + always on bits + > +32d7 : d96602 > cmp absflo,y ;test flags + > trap_ne +32da : d0fe > bne * ;failed not equal (non zero) + > + +32dc : 88 dey +32dd : 10e6 bpl tora14 +32df : a003 ldy #3 +32e1 : tora15 + set_ay absORa,$ff + > load_flag $ff +32e1 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +32e3 : 48 > pha ;use stack to load status +32e4 : b95602 > lda absORa,y ;precharge accu +32e7 : 28 > plp + +32e8 : 114a ora (indOR),y + tst_ay absrlo,absflo,$ff-fnz +32ea : 08 > php ;save flags +32eb : d96202 > cmp absrlo,y ;test result + > trap_ne ; +32ee : d0fe > bne * ;failed not equal (non zero) + > +32f0 : 68 > pla ;load status + > eor_flag $ff-fnz +32f1 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits + > +32f3 : d96602 > cmp absflo,y ;test flags + > trap_ne +32f6 : d0fe > bne * ;failed not equal (non zero) + > + +32f8 : 88 dey +32f9 : 10e6 bpl tora15 + if I_flag = 3 +32fb : 58 cli + endif + next_test +32fc : ad0002 > lda test_case ;previous test +32ff : c928 > cmp #test_num + > trap_ne ;test is out of sequence +3301 : d0fe > bne * ;failed not equal (non zero) + > +0029 = >test_num = test_num + 1 +3303 : a929 > lda #test_num ;*** next tests' number +3305 : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; full binary add/subtract test + ; iterates through all combinations of operands and carry input + ; uses increments/decrements to predict result & result flags +3308 : d8 cld +3309 : a20e ldx #ad2 ;for indexed test +330b : a0ff ldy #$ff ;max range +330d : a900 lda #0 ;start with adding zeroes & no carry +330f : 850c sta adfc ;carry in - for diag +3311 : 850d sta ad1 ;operand 1 - accumulator +3313 : 850e sta ad2 ;operand 2 - memory or immediate +3315 : 8d0302 sta ada2 ;non zp +3318 : 850f sta adrl ;expected result bits 0-7 +331a : 8510 sta adrh ;expected result bit 8 (carry out) +331c : a9ff lda #$ff ;complemented operand 2 for subtract +331e : 8512 sta sb2 +3320 : 8d0402 sta sba2 ;non zp +3323 : a902 lda #2 ;expected Z-flag +3325 : 8511 sta adrf +3327 : 18 tadd clc ;test with carry clear +3328 : 20a235 jsr chkadd +332b : e60c inc adfc ;now with carry +332d : e60f inc adrl ;result +1 +332f : 08 php ;save N & Z from low result +3330 : 08 php +3331 : 68 pla ;accu holds expected flags +3332 : 2982 and #$82 ;mask N & Z +3334 : 28 plp +3335 : d002 bne tadd1 +3337 : e610 inc adrh ;result bit 8 - carry +3339 : 0510 tadd1 ora adrh ;merge C to expected flags +333b : 8511 sta adrf ;save expected flags except overflow +333d : 38 sec ;test with carry set +333e : 20a235 jsr chkadd +3341 : c60c dec adfc ;same for operand +1 but no carry +3343 : e60d inc ad1 +3345 : d0e0 bne tadd ;iterate op1 +3347 : a900 lda #0 ;preset result to op2 when op1 = 0 +3349 : 8510 sta adrh +334b : ee0302 inc ada2 +334e : e60e inc ad2 +3350 : 08 php ;save NZ as operand 2 becomes the new result +3351 : 68 pla +3352 : 2982 and #$82 ;mask N00000Z0 +3354 : 8511 sta adrf ;no need to check carry as we are adding to 0 +3356 : c612 dec sb2 ;complement subtract operand 2 +3358 : ce0402 dec sba2 +335b : a50e lda ad2 +335d : 850f sta adrl +335f : d0c6 bne tadd ;iterate op2 + if disable_decimal < 1 + next_test +3361 : ad0002 > lda test_case ;previous test +3364 : c929 > cmp #test_num + > trap_ne ;test is out of sequence +3366 : d0fe > bne * ;failed not equal (non zero) + > +002a = >test_num = test_num + 1 +3368 : a92a > lda #test_num ;*** next tests' number +336a : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; decimal add/subtract test + ; *** WARNING - tests documented behavior only! *** + ; only valid BCD operands are tested, N V Z flags are ignored + ; iterates through all valid combinations of operands and carry input + ; uses increments/decrements to predict result & carry flag +336d : f8 sed +336e : a20e ldx #ad2 ;for indexed test +3370 : a0ff ldy #$ff ;max range +3372 : a999 lda #$99 ;start with adding 99 to 99 with carry +3374 : 850d sta ad1 ;operand 1 - accumulator +3376 : 850e sta ad2 ;operand 2 - memory or immediate +3378 : 8d0302 sta ada2 ;non zp +337b : 850f sta adrl ;expected result bits 0-7 +337d : a901 lda #1 ;set carry in & out +337f : 850c sta adfc ;carry in - for diag +3381 : 8510 sta adrh ;expected result bit 8 (carry out) +3383 : a900 lda #0 ;complemented operand 2 for subtract +3385 : 8512 sta sb2 +3387 : 8d0402 sta sba2 ;non zp +338a : 38 tdad sec ;test with carry set +338b : 206f34 jsr chkdad +338e : c60c dec adfc ;now with carry clear +3390 : a50f lda adrl ;decimal adjust result +3392 : d008 bne tdad1 ;skip clear carry & preset result 99 (9A-1) +3394 : c610 dec adrh +3396 : a999 lda #$99 +3398 : 850f sta adrl +339a : d012 bne tdad3 +339c : 290f tdad1 and #$f ;lower nibble mask +339e : d00c bne tdad2 ;no decimal adjust needed +33a0 : c60f dec adrl ;decimal adjust (?0-6) +33a2 : c60f dec adrl +33a4 : c60f dec adrl +33a6 : c60f dec adrl +33a8 : c60f dec adrl +33aa : c60f dec adrl +33ac : c60f tdad2 dec adrl ;result -1 +33ae : 18 tdad3 clc ;test with carry clear +33af : 206f34 jsr chkdad +33b2 : e60c inc adfc ;same for operand -1 but with carry +33b4 : a50d lda ad1 ;decimal adjust operand 1 +33b6 : f015 beq tdad5 ;iterate operand 2 +33b8 : 290f and #$f ;lower nibble mask +33ba : d00c bne tdad4 ;skip decimal adjust +33bc : c60d dec ad1 ;decimal adjust (?0-6) +33be : c60d dec ad1 +33c0 : c60d dec ad1 +33c2 : c60d dec ad1 +33c4 : c60d dec ad1 +33c6 : c60d dec ad1 +33c8 : c60d tdad4 dec ad1 ;operand 1 -1 +33ca : 4c8a33 jmp tdad ;iterate op1 + +33cd : a999 tdad5 lda #$99 ;precharge op1 max +33cf : 850d sta ad1 +33d1 : a50e lda ad2 ;decimal adjust operand 2 +33d3 : f030 beq tdad7 ;end of iteration +33d5 : 290f and #$f ;lower nibble mask +33d7 : d018 bne tdad6 ;skip decimal adjust +33d9 : c60e dec ad2 ;decimal adjust (?0-6) +33db : c60e dec ad2 +33dd : c60e dec ad2 +33df : c60e dec ad2 +33e1 : c60e dec ad2 +33e3 : c60e dec ad2 +33e5 : e612 inc sb2 ;complemented decimal adjust for subtract (?9+6) +33e7 : e612 inc sb2 +33e9 : e612 inc sb2 +33eb : e612 inc sb2 +33ed : e612 inc sb2 +33ef : e612 inc sb2 +33f1 : c60e tdad6 dec ad2 ;operand 2 -1 +33f3 : e612 inc sb2 ;complemented operand for subtract +33f5 : a512 lda sb2 +33f7 : 8d0402 sta sba2 ;copy as non zp operand +33fa : a50e lda ad2 +33fc : 8d0302 sta ada2 ;copy as non zp operand +33ff : 850f sta adrl ;new result since op1+carry=00+carry +op2=op2 +3401 : e610 inc adrh ;result carry +3403 : d085 bne tdad ;iterate op2 +3405 : tdad7 + next_test +3405 : ad0002 > lda test_case ;previous test +3408 : c92a > cmp #test_num + > trap_ne ;test is out of sequence +340a : d0fe > bne * ;failed not equal (non zero) + > +002b = >test_num = test_num + 1 +340c : a92b > lda #test_num ;*** next tests' number +340e : 8d0002 > sta test_case + > ;check_ram ;uncomment to find altered RAM after each test + + + ; decimal/binary switch test + ; tests CLD, SED, PLP, RTI to properly switch between decimal & binary opcode + ; tables +3411 : 18 clc +3412 : d8 cld +3413 : 08 php +3414 : a955 lda #$55 +3416 : 6955 adc #$55 +3418 : c9aa cmp #$aa + trap_ne ;expected binary result after cld +341a : d0fe > bne * ;failed not equal (non zero) + +341c : 18 clc +341d : f8 sed +341e : 08 php +341f : a955 lda #$55 +3421 : 6955 adc #$55 +3423 : c910 cmp #$10 + trap_ne ;expected decimal result after sed +3425 : d0fe > bne * ;failed not equal (non zero) + +3427 : d8 cld +3428 : 28 plp +3429 : a955 lda #$55 +342b : 6955 adc #$55 +342d : c910 cmp #$10 + trap_ne ;expected decimal result after plp D=1 +342f : d0fe > bne * ;failed not equal (non zero) + +3431 : 28 plp +3432 : a955 lda #$55 +3434 : 6955 adc #$55 +3436 : c9aa cmp #$aa + trap_ne ;expected binary result after plp D=0 +3438 : d0fe > bne * ;failed not equal (non zero) + +343a : 18 clc +343b : a934 lda #hi bin_rti_ret ;emulated interrupt for rti +343d : 48 pha +343e : a955 lda #lo bin_rti_ret +3440 : 48 pha +3441 : 08 php +3442 : f8 sed +3443 : a934 lda #hi dec_rti_ret ;emulated interrupt for rti +3445 : 48 pha +3446 : a94c lda #lo dec_rti_ret +3448 : 48 pha +3449 : 08 php +344a : d8 cld +344b : 40 rti +344c : dec_rti_ret +344c : a955 lda #$55 +344e : 6955 adc #$55 +3450 : c910 cmp #$10 + trap_ne ;expected decimal result after rti D=1 +3452 : d0fe > bne * ;failed not equal (non zero) + +3454 : 40 rti +3455 : bin_rti_ret +3455 : a955 lda #$55 +3457 : 6955 adc #$55 +3459 : c9aa cmp #$aa + trap_ne ;expected binary result after rti D=0 +345b : d0fe > bne * ;failed not equal (non zero) + + endif + +345d : ad0002 lda test_case +3460 : c92b cmp #test_num + trap_ne ;previous test is out of sequence +3462 : d0fe > bne * ;failed not equal (non zero) + +3464 : a9f0 lda #$f0 ;mark opcode testing complete +3466 : 8d0002 sta test_case + + ; final RAM integrity test + ; verifies that none of the previous tests has altered RAM outside of the + ; designated write areas. + check_ram + > ;RAM check disabled - RAM size not set + + ; *** DEBUG INFO *** + ; to debug checksum errors uncomment check_ram in the next_test macro to + ; narrow down the responsible opcode. + ; may give false errors when monitor, OS or other background activity is + ; allowed during previous tests. + + + ; S U C C E S S ************************************************ + ; ------------- + success ;if you get here everything went well +3469 : 4c6934 > jmp * ;test passed, no errors + + ; ------------- + ; S U C C E S S ************************************************ +346c : 4c0004 jmp start ;run again + + if disable_decimal < 1 + ; core subroutine of the decimal add/subtract test + ; *** WARNING - tests documented behavior only! *** + ; only valid BCD operands are tested, N V Z flags are ignored + ; iterates through all valid combinations of operands and carry input + ; uses increments/decrements to predict result & carry flag +346f : chkdad + ; decimal ADC / SBC zp +346f : 08 php ;save carry for subtract +3470 : a50d lda ad1 +3472 : 650e adc ad2 ;perform add +3474 : 08 php +3475 : c50f cmp adrl ;check result + trap_ne ;bad result +3477 : d0fe > bne * ;failed not equal (non zero) + +3479 : 68 pla ;check flags +347a : 2901 and #1 ;mask carry +347c : c510 cmp adrh + trap_ne ;bad carry +347e : d0fe > bne * ;failed not equal (non zero) + +3480 : 28 plp +3481 : 08 php ;save carry for next add +3482 : a50d lda ad1 +3484 : e512 sbc sb2 ;perform subtract +3486 : 08 php +3487 : c50f cmp adrl ;check result + trap_ne ;bad result +3489 : d0fe > bne * ;failed not equal (non zero) + +348b : 68 pla ;check flags +348c : 2901 and #1 ;mask carry +348e : c510 cmp adrh + trap_ne ;bad flags +3490 : d0fe > bne * ;failed not equal (non zero) + +3492 : 28 plp + ; decimal ADC / SBC abs +3493 : 08 php ;save carry for subtract +3494 : a50d lda ad1 +3496 : 6d0302 adc ada2 ;perform add +3499 : 08 php +349a : c50f cmp adrl ;check result + trap_ne ;bad result +349c : d0fe > bne * ;failed not equal (non zero) + +349e : 68 pla ;check flags +349f : 2901 and #1 ;mask carry +34a1 : c510 cmp adrh + trap_ne ;bad carry +34a3 : d0fe > bne * ;failed not equal (non zero) + +34a5 : 28 plp +34a6 : 08 php ;save carry for next add +34a7 : a50d lda ad1 +34a9 : ed0402 sbc sba2 ;perform subtract +34ac : 08 php +34ad : c50f cmp adrl ;check result + trap_ne ;bad result +34af : d0fe > bne * ;failed not equal (non zero) + +34b1 : 68 pla ;check flags +34b2 : 2901 and #1 ;mask carry +34b4 : c510 cmp adrh + trap_ne ;bad carry +34b6 : d0fe > bne * ;failed not equal (non zero) + +34b8 : 28 plp + ; decimal ADC / SBC # +34b9 : 08 php ;save carry for subtract +34ba : a50e lda ad2 +34bc : 8d1202 sta ex_adci+1 ;set ADC # operand +34bf : a50d lda ad1 +34c1 : 201102 jsr ex_adci ;execute ADC # in RAM +34c4 : 08 php +34c5 : c50f cmp adrl ;check result + trap_ne ;bad result +34c7 : d0fe > bne * ;failed not equal (non zero) + +34c9 : 68 pla ;check flags +34ca : 2901 and #1 ;mask carry +34cc : c510 cmp adrh + trap_ne ;bad carry +34ce : d0fe > bne * ;failed not equal (non zero) + +34d0 : 28 plp +34d1 : 08 php ;save carry for next add +34d2 : a512 lda sb2 +34d4 : 8d1502 sta ex_sbci+1 ;set SBC # operand +34d7 : a50d lda ad1 +34d9 : 201402 jsr ex_sbci ;execute SBC # in RAM +34dc : 08 php +34dd : c50f cmp adrl ;check result + trap_ne ;bad result +34df : d0fe > bne * ;failed not equal (non zero) + +34e1 : 68 pla ;check flags +34e2 : 2901 and #1 ;mask carry +34e4 : c510 cmp adrh + trap_ne ;bad carry +34e6 : d0fe > bne * ;failed not equal (non zero) + +34e8 : 28 plp + ; decimal ADC / SBC zp,x +34e9 : 08 php ;save carry for subtract +34ea : a50d lda ad1 +34ec : 7500 adc 0,x ;perform add +34ee : 08 php +34ef : c50f cmp adrl ;check result + trap_ne ;bad result +34f1 : d0fe > bne * ;failed not equal (non zero) + +34f3 : 68 pla ;check flags +34f4 : 2901 and #1 ;mask carry +34f6 : c510 cmp adrh + trap_ne ;bad carry +34f8 : d0fe > bne * ;failed not equal (non zero) + +34fa : 28 plp +34fb : 08 php ;save carry for next add +34fc : a50d lda ad1 +34fe : f504 sbc sb2-ad2,x ;perform subtract +3500 : 08 php +3501 : c50f cmp adrl ;check result + trap_ne ;bad result +3503 : d0fe > bne * ;failed not equal (non zero) + +3505 : 68 pla ;check flags +3506 : 2901 and #1 ;mask carry +3508 : c510 cmp adrh + trap_ne ;bad carry +350a : d0fe > bne * ;failed not equal (non zero) + +350c : 28 plp + ; decimal ADC / SBC abs,x +350d : 08 php ;save carry for subtract +350e : a50d lda ad1 +3510 : 7df501 adc ada2-ad2,x ;perform add +3513 : 08 php +3514 : c50f cmp adrl ;check result + trap_ne ;bad result +3516 : d0fe > bne * ;failed not equal (non zero) + +3518 : 68 pla ;check flags +3519 : 2901 and #1 ;mask carry +351b : c510 cmp adrh + trap_ne ;bad carry +351d : d0fe > bne * ;failed not equal (non zero) + +351f : 28 plp +3520 : 08 php ;save carry for next add +3521 : a50d lda ad1 +3523 : fdf601 sbc sba2-ad2,x ;perform subtract +3526 : 08 php +3527 : c50f cmp adrl ;check result + trap_ne ;bad result +3529 : d0fe > bne * ;failed not equal (non zero) + +352b : 68 pla ;check flags +352c : 2901 and #1 ;mask carry +352e : c510 cmp adrh + trap_ne ;bad carry +3530 : d0fe > bne * ;failed not equal (non zero) + +3532 : 28 plp + ; decimal ADC / SBC abs,y +3533 : 08 php ;save carry for subtract +3534 : a50d lda ad1 +3536 : 790401 adc ada2-$ff,y ;perform add +3539 : 08 php +353a : c50f cmp adrl ;check result + trap_ne ;bad result +353c : d0fe > bne * ;failed not equal (non zero) + +353e : 68 pla ;check flags +353f : 2901 and #1 ;mask carry +3541 : c510 cmp adrh + trap_ne ;bad carry +3543 : d0fe > bne * ;failed not equal (non zero) + +3545 : 28 plp +3546 : 08 php ;save carry for next add +3547 : a50d lda ad1 +3549 : f90501 sbc sba2-$ff,y ;perform subtract +354c : 08 php +354d : c50f cmp adrl ;check result + trap_ne ;bad result +354f : d0fe > bne * ;failed not equal (non zero) + +3551 : 68 pla ;check flags +3552 : 2901 and #1 ;mask carry +3554 : c510 cmp adrh + trap_ne ;bad carry +3556 : d0fe > bne * ;failed not equal (non zero) + +3558 : 28 plp + ; decimal ADC / SBC (zp,x) +3559 : 08 php ;save carry for subtract +355a : a50d lda ad1 +355c : 6144 adc (lo adi2-ad2,x) ;perform add +355e : 08 php +355f : c50f cmp adrl ;check result + trap_ne ;bad result +3561 : d0fe > bne * ;failed not equal (non zero) + +3563 : 68 pla ;check flags +3564 : 2901 and #1 ;mask carry +3566 : c510 cmp adrh + trap_ne ;bad carry +3568 : d0fe > bne * ;failed not equal (non zero) + +356a : 28 plp +356b : 08 php ;save carry for next add +356c : a50d lda ad1 +356e : e146 sbc (lo sbi2-ad2,x) ;perform subtract +3570 : 08 php +3571 : c50f cmp adrl ;check result + trap_ne ;bad result +3573 : d0fe > bne * ;failed not equal (non zero) + +3575 : 68 pla ;check flags +3576 : 2901 and #1 ;mask carry +3578 : c510 cmp adrh + trap_ne ;bad carry +357a : d0fe > bne * ;failed not equal (non zero) + +357c : 28 plp + ; decimal ADC / SBC (abs),y +357d : 08 php ;save carry for subtract +357e : a50d lda ad1 +3580 : 7156 adc (adiy2),y ;perform add +3582 : 08 php +3583 : c50f cmp adrl ;check result + trap_ne ;bad result +3585 : d0fe > bne * ;failed not equal (non zero) + +3587 : 68 pla ;check flags +3588 : 2901 and #1 ;mask carry +358a : c510 cmp adrh + trap_ne ;bad carry +358c : d0fe > bne * ;failed not equal (non zero) + +358e : 28 plp +358f : 08 php ;save carry for next add +3590 : a50d lda ad1 +3592 : f158 sbc (sbiy2),y ;perform subtract +3594 : 08 php +3595 : c50f cmp adrl ;check result + trap_ne ;bad result +3597 : d0fe > bne * ;failed not equal (non zero) + +3599 : 68 pla ;check flags +359a : 2901 and #1 ;mask carry +359c : c510 cmp adrh + trap_ne ;bad carry +359e : d0fe > bne * ;failed not equal (non zero) + +35a0 : 28 plp +35a1 : 60 rts + endif + + ; core subroutine of the full binary add/subtract test + ; iterates through all combinations of operands and carry input + ; uses increments/decrements to predict result & result flags +35a2 : a511 chkadd lda adrf ;add V-flag if overflow +35a4 : 2983 and #$83 ;keep N-----ZC / clear V +35a6 : 48 pha +35a7 : a50d lda ad1 ;test sign unequal between operands +35a9 : 450e eor ad2 +35ab : 300a bmi ckad1 ;no overflow possible - operands have different sign +35ad : a50d lda ad1 ;test sign equal between operands and result +35af : 450f eor adrl +35b1 : 1004 bpl ckad1 ;no overflow occured - operand and result have same sign +35b3 : 68 pla +35b4 : 0940 ora #$40 ;set V +35b6 : 48 pha +35b7 : 68 ckad1 pla +35b8 : 8511 sta adrf ;save expected flags + ; binary ADC / SBC zp +35ba : 08 php ;save carry for subtract +35bb : a50d lda ad1 +35bd : 650e adc ad2 ;perform add +35bf : 08 php +35c0 : c50f cmp adrl ;check result + trap_ne ;bad result +35c2 : d0fe > bne * ;failed not equal (non zero) + +35c4 : 68 pla ;check flags +35c5 : 29c3 and #$c3 ;mask NV----ZC +35c7 : c511 cmp adrf + trap_ne ;bad flags +35c9 : d0fe > bne * ;failed not equal (non zero) + +35cb : 28 plp +35cc : 08 php ;save carry for next add +35cd : a50d lda ad1 +35cf : e512 sbc sb2 ;perform subtract +35d1 : 08 php +35d2 : c50f cmp adrl ;check result + trap_ne ;bad result +35d4 : d0fe > bne * ;failed not equal (non zero) + +35d6 : 68 pla ;check flags +35d7 : 29c3 and #$c3 ;mask NV----ZC +35d9 : c511 cmp adrf + trap_ne ;bad flags +35db : d0fe > bne * ;failed not equal (non zero) + +35dd : 28 plp + ; binary ADC / SBC abs +35de : 08 php ;save carry for subtract +35df : a50d lda ad1 +35e1 : 6d0302 adc ada2 ;perform add +35e4 : 08 php +35e5 : c50f cmp adrl ;check result + trap_ne ;bad result +35e7 : d0fe > bne * ;failed not equal (non zero) + +35e9 : 68 pla ;check flags +35ea : 29c3 and #$c3 ;mask NV----ZC +35ec : c511 cmp adrf + trap_ne ;bad flags +35ee : d0fe > bne * ;failed not equal (non zero) + +35f0 : 28 plp +35f1 : 08 php ;save carry for next add +35f2 : a50d lda ad1 +35f4 : ed0402 sbc sba2 ;perform subtract +35f7 : 08 php +35f8 : c50f cmp adrl ;check result + trap_ne ;bad result +35fa : d0fe > bne * ;failed not equal (non zero) + +35fc : 68 pla ;check flags +35fd : 29c3 and #$c3 ;mask NV----ZC +35ff : c511 cmp adrf + trap_ne ;bad flags +3601 : d0fe > bne * ;failed not equal (non zero) + +3603 : 28 plp + ; binary ADC / SBC # +3604 : 08 php ;save carry for subtract +3605 : a50e lda ad2 +3607 : 8d1202 sta ex_adci+1 ;set ADC # operand +360a : a50d lda ad1 +360c : 201102 jsr ex_adci ;execute ADC # in RAM +360f : 08 php +3610 : c50f cmp adrl ;check result + trap_ne ;bad result +3612 : d0fe > bne * ;failed not equal (non zero) + +3614 : 68 pla ;check flags +3615 : 29c3 and #$c3 ;mask NV----ZC +3617 : c511 cmp adrf + trap_ne ;bad flags +3619 : d0fe > bne * ;failed not equal (non zero) + +361b : 28 plp +361c : 08 php ;save carry for next add +361d : a512 lda sb2 +361f : 8d1502 sta ex_sbci+1 ;set SBC # operand +3622 : a50d lda ad1 +3624 : 201402 jsr ex_sbci ;execute SBC # in RAM +3627 : 08 php +3628 : c50f cmp adrl ;check result + trap_ne ;bad result +362a : d0fe > bne * ;failed not equal (non zero) + +362c : 68 pla ;check flags +362d : 29c3 and #$c3 ;mask NV----ZC +362f : c511 cmp adrf + trap_ne ;bad flags +3631 : d0fe > bne * ;failed not equal (non zero) + +3633 : 28 plp + ; binary ADC / SBC zp,x +3634 : 08 php ;save carry for subtract +3635 : a50d lda ad1 +3637 : 7500 adc 0,x ;perform add +3639 : 08 php +363a : c50f cmp adrl ;check result + trap_ne ;bad result +363c : d0fe > bne * ;failed not equal (non zero) + +363e : 68 pla ;check flags +363f : 29c3 and #$c3 ;mask NV----ZC +3641 : c511 cmp adrf + trap_ne ;bad flags +3643 : d0fe > bne * ;failed not equal (non zero) + +3645 : 28 plp +3646 : 08 php ;save carry for next add +3647 : a50d lda ad1 +3649 : f504 sbc sb2-ad2,x ;perform subtract +364b : 08 php +364c : c50f cmp adrl ;check result + trap_ne ;bad result +364e : d0fe > bne * ;failed not equal (non zero) + +3650 : 68 pla ;check flags +3651 : 29c3 and #$c3 ;mask NV----ZC +3653 : c511 cmp adrf + trap_ne ;bad flags +3655 : d0fe > bne * ;failed not equal (non zero) + +3657 : 28 plp + ; binary ADC / SBC abs,x +3658 : 08 php ;save carry for subtract +3659 : a50d lda ad1 +365b : 7df501 adc ada2-ad2,x ;perform add +365e : 08 php +365f : c50f cmp adrl ;check result + trap_ne ;bad result +3661 : d0fe > bne * ;failed not equal (non zero) + +3663 : 68 pla ;check flags +3664 : 29c3 and #$c3 ;mask NV----ZC +3666 : c511 cmp adrf + trap_ne ;bad flags +3668 : d0fe > bne * ;failed not equal (non zero) + +366a : 28 plp +366b : 08 php ;save carry for next add +366c : a50d lda ad1 +366e : fdf601 sbc sba2-ad2,x ;perform subtract +3671 : 08 php +3672 : c50f cmp adrl ;check result + trap_ne ;bad result +3674 : d0fe > bne * ;failed not equal (non zero) + +3676 : 68 pla ;check flags +3677 : 29c3 and #$c3 ;mask NV----ZC +3679 : c511 cmp adrf + trap_ne ;bad flags +367b : d0fe > bne * ;failed not equal (non zero) + +367d : 28 plp + ; binary ADC / SBC abs,y +367e : 08 php ;save carry for subtract +367f : a50d lda ad1 +3681 : 790401 adc ada2-$ff,y ;perform add +3684 : 08 php +3685 : c50f cmp adrl ;check result + trap_ne ;bad result +3687 : d0fe > bne * ;failed not equal (non zero) + +3689 : 68 pla ;check flags +368a : 29c3 and #$c3 ;mask NV----ZC +368c : c511 cmp adrf + trap_ne ;bad flags +368e : d0fe > bne * ;failed not equal (non zero) + +3690 : 28 plp +3691 : 08 php ;save carry for next add +3692 : a50d lda ad1 +3694 : f90501 sbc sba2-$ff,y ;perform subtract +3697 : 08 php +3698 : c50f cmp adrl ;check result + trap_ne ;bad result +369a : d0fe > bne * ;failed not equal (non zero) + +369c : 68 pla ;check flags +369d : 29c3 and #$c3 ;mask NV----ZC +369f : c511 cmp adrf + trap_ne ;bad flags +36a1 : d0fe > bne * ;failed not equal (non zero) + +36a3 : 28 plp + ; binary ADC / SBC (zp,x) +36a4 : 08 php ;save carry for subtract +36a5 : a50d lda ad1 +36a7 : 6144 adc (lo adi2-ad2,x) ;perform add +36a9 : 08 php +36aa : c50f cmp adrl ;check result + trap_ne ;bad result +36ac : d0fe > bne * ;failed not equal (non zero) + +36ae : 68 pla ;check flags +36af : 29c3 and #$c3 ;mask NV----ZC +36b1 : c511 cmp adrf + trap_ne ;bad flags +36b3 : d0fe > bne * ;failed not equal (non zero) + +36b5 : 28 plp +36b6 : 08 php ;save carry for next add +36b7 : a50d lda ad1 +36b9 : e146 sbc (lo sbi2-ad2,x) ;perform subtract +36bb : 08 php +36bc : c50f cmp adrl ;check result + trap_ne ;bad result +36be : d0fe > bne * ;failed not equal (non zero) + +36c0 : 68 pla ;check flags +36c1 : 29c3 and #$c3 ;mask NV----ZC +36c3 : c511 cmp adrf + trap_ne ;bad flags +36c5 : d0fe > bne * ;failed not equal (non zero) + +36c7 : 28 plp + ; binary ADC / SBC (abs),y +36c8 : 08 php ;save carry for subtract +36c9 : a50d lda ad1 +36cb : 7156 adc (adiy2),y ;perform add +36cd : 08 php +36ce : c50f cmp adrl ;check result + trap_ne ;bad result +36d0 : d0fe > bne * ;failed not equal (non zero) + +36d2 : 68 pla ;check flags +36d3 : 29c3 and #$c3 ;mask NV----ZC +36d5 : c511 cmp adrf + trap_ne ;bad flags +36d7 : d0fe > bne * ;failed not equal (non zero) + +36d9 : 28 plp +36da : 08 php ;save carry for next add +36db : a50d lda ad1 +36dd : f158 sbc (sbiy2),y ;perform subtract +36df : 08 php +36e0 : c50f cmp adrl ;check result + trap_ne ;bad result +36e2 : d0fe > bne * ;failed not equal (non zero) + +36e4 : 68 pla ;check flags +36e5 : 29c3 and #$c3 ;mask NV----ZC +36e7 : c511 cmp adrf + trap_ne ;bad flags +36e9 : d0fe > bne * ;failed not equal (non zero) + +36eb : 28 plp +36ec : 60 rts + + ; target for the jump absolute test +36ed : 88 dey +36ee : 88 dey +36ef : test_far +36ef : 08 php ;either SP or Y count will fail, if we do not hit +36f0 : 88 dey +36f1 : 88 dey +36f2 : 88 dey +36f3 : 28 plp + trap_cs ;flags loaded? +36f4 : b0fe > bcs * ;failed carry set + + trap_vs +36f6 : 70fe > bvs * ;failed overflow set + + trap_mi +36f8 : 30fe > bmi * ;failed minus (bit 7 set) + + trap_eq +36fa : f0fe > beq * ;failed equal (zero) + +36fc : c946 cmp #'F' ;registers loaded? + trap_ne +36fe : d0fe > bne * ;failed not equal (non zero) + +3700 : e041 cpx #'A' + trap_ne +3702 : d0fe > bne * ;failed not equal (non zero) + +3704 : c04f cpy #('R'-3) + trap_ne +3706 : d0fe > bne * ;failed not equal (non zero) + +3708 : 48 pha ;save a,x +3709 : 8a txa +370a : 48 pha +370b : ba tsx +370c : e0fd cpx #$fd ;check SP + trap_ne +370e : d0fe > bne * ;failed not equal (non zero) + +3710 : 68 pla ;restore x +3711 : aa tax + set_stat $ff + > load_flag $ff +3712 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +3714 : 48 > pha ;use stack to load status +3715 : 28 > plp + +3716 : 68 pla ;restore a +3717 : e8 inx ;return registers with modifications +3718 : 49aa eor #$aa ;N=1, V=1, Z=0, C=1 +371a : 4c0f09 jmp far_ret + + ; target for the jump indirect test +371d : 00 align +371e : 2737 ptr_tst_ind dw test_ind +3720 : 6409 ptr_ind_ret dw ind_ret + trap ;runover protection +3722 : 4c2237 > jmp * ;failed anyway + +3725 : 88 dey +3726 : 88 dey +3727 : test_ind +3727 : 08 php ;either SP or Y count will fail, if we do not hit +3728 : 88 dey +3729 : 88 dey +372a : 88 dey +372b : 28 plp + trap_cs ;flags loaded? +372c : b0fe > bcs * ;failed carry set + + trap_vs +372e : 70fe > bvs * ;failed overflow set + + trap_mi +3730 : 30fe > bmi * ;failed minus (bit 7 set) + + trap_eq +3732 : f0fe > beq * ;failed equal (zero) + +3734 : c949 cmp #'I' ;registers loaded? + trap_ne +3736 : d0fe > bne * ;failed not equal (non zero) + +3738 : e04e cpx #'N' + trap_ne +373a : d0fe > bne * ;failed not equal (non zero) + +373c : c041 cpy #('D'-3) + trap_ne +373e : d0fe > bne * ;failed not equal (non zero) + +3740 : 48 pha ;save a,x +3741 : 8a txa +3742 : 48 pha +3743 : ba tsx +3744 : e0fd cpx #$fd ;check SP + trap_ne +3746 : d0fe > bne * ;failed not equal (non zero) + +3748 : 68 pla ;restore x +3749 : aa tax + set_stat $ff + > load_flag $ff +374a : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +374c : 48 > pha ;use stack to load status +374d : 28 > plp + +374e : 68 pla ;restore a +374f : e8 inx ;return registers with modifications +3750 : 49aa eor #$aa ;N=1, V=1, Z=0, C=1 +3752 : 6c2037 jmp (ptr_ind_ret) + trap ;runover protection +3755 : 4c5537 > jmp * ;failed anyway + +3758 : 4c0004 jmp start ;catastrophic error - cannot continue + + ; target for the jump subroutine test +375b : 88 dey +375c : 88 dey +375d : test_jsr +375d : 08 php ;either SP or Y count will fail, if we do not hit +375e : 88 dey +375f : 88 dey +3760 : 88 dey +3761 : 28 plp + trap_cs ;flags loaded? +3762 : b0fe > bcs * ;failed carry set + + trap_vs +3764 : 70fe > bvs * ;failed overflow set + + trap_mi +3766 : 30fe > bmi * ;failed minus (bit 7 set) + + trap_eq +3768 : f0fe > beq * ;failed equal (zero) + +376a : c94a cmp #'J' ;registers loaded? + trap_ne +376c : d0fe > bne * ;failed not equal (non zero) + +376e : e053 cpx #'S' + trap_ne +3770 : d0fe > bne * ;failed not equal (non zero) + +3772 : c04f cpy #('R'-3) + trap_ne +3774 : d0fe > bne * ;failed not equal (non zero) + +3776 : 48 pha ;save a,x +3777 : 8a txa +3778 : 48 pha +3779 : ba tsx ;sp -4? (return addr,a,x) +377a : e0fb cpx #$fb + trap_ne +377c : d0fe > bne * ;failed not equal (non zero) + +377e : adff01 lda $1ff ;propper return on stack +3781 : c909 cmp #hi(jsr_ret) + trap_ne +3783 : d0fe > bne * ;failed not equal (non zero) + +3785 : adfe01 lda $1fe +3788 : c99a cmp #lo(jsr_ret) + trap_ne +378a : d0fe > bne * ;failed not equal (non zero) + + set_stat $ff + > load_flag $ff +378c : a9ff > lda #$ff ;allow test to change I-flag (no mask) + > +378e : 48 > pha ;use stack to load status +378f : 28 > plp + +3790 : 68 pla ;pull x,a +3791 : aa tax +3792 : 68 pla +3793 : e8 inx ;return registers with modifications +3794 : 49aa eor #$aa ;N=1, V=1, Z=0, C=1 +3796 : 60 rts + trap ;runover protection +3797 : 4c9737 > jmp * ;failed anyway + +379a : 4c0004 jmp start ;catastrophic error - cannot continue + + ;trap in case of unexpected IRQ, NMI, BRK, RESET - BRK test target +379d : nmi_trap + trap ;check stack for conditions at NMI +379d : 4c9d37 > jmp * ;failed anyway + +37a0 : 4c0004 jmp start ;catastrophic error - cannot continue +37a3 : res_trap + trap ;unexpected RESET +37a3 : 4ca337 > jmp * ;failed anyway + +37a6 : 4c0004 jmp start ;catastrophic error - cannot continue + +37a9 : 88 dey +37aa : 88 dey +37ab : irq_trap ;BRK test or unextpected BRK or IRQ +37ab : 08 php ;either SP or Y count will fail, if we do not hit +37ac : 88 dey +37ad : 88 dey +37ae : 88 dey + ;next traps could be caused by unexpected BRK or IRQ + ;check stack for BREAK and originating location + ;possible jump/branch into weeds (uninitialized space) +37af : c9bd cmp #$ff-'B' ;BRK pass 2 registers loaded? +37b1 : f042 beq break2 +37b3 : c942 cmp #'B' ;BRK pass 1 registers loaded? + trap_ne +37b5 : d0fe > bne * ;failed not equal (non zero) + +37b7 : e052 cpx #'R' + trap_ne +37b9 : d0fe > bne * ;failed not equal (non zero) + +37bb : c048 cpy #'K'-3 + trap_ne +37bd : d0fe > bne * ;failed not equal (non zero) + +37bf : 850a sta irq_a ;save registers during break test +37c1 : 860b stx irq_x +37c3 : ba tsx ;test break on stack +37c4 : bd0201 lda $102,x + cmp_flag 0 ;break test should have B=1 & unused=1 on stack +37c7 : c930 > cmp #(0 |fao)&m8 ;expected flags + always on bits + + trap_ne ; - no break flag on stack +37c9 : d0fe > bne * ;failed not equal (non zero) + +37cb : 68 pla + cmp_flag intdis ;should have added interrupt disable +37cc : c934 > cmp #(intdis |fao)&m8 ;expected flags + always on bits + + trap_ne +37ce : d0fe > bne * ;failed not equal (non zero) + +37d0 : ba tsx +37d1 : e0fc cpx #$fc ;sp -3? (return addr, flags) + trap_ne +37d3 : d0fe > bne * ;failed not equal (non zero) + +37d5 : adff01 lda $1ff ;propper return on stack +37d8 : c909 cmp #hi(brk_ret0) + trap_ne +37da : d0fe > bne * ;failed not equal (non zero) + +37dc : adfe01 lda $1fe +37df : c9d1 cmp #lo(brk_ret0) + trap_ne +37e1 : d0fe > bne * ;failed not equal (non zero) + + load_flag $ff +37e3 : a9ff > lda #$ff ;allow test to change I-flag (no mask) + +37e5 : 48 pha +37e6 : a60b ldx irq_x +37e8 : e8 inx ;return registers with modifications +37e9 : a50a lda irq_a +37eb : 49aa eor #$aa +37ed : 28 plp ;N=1, V=1, Z=1, C=1 but original flags should be restored +37ee : 40 rti + trap ;runover protection +37ef : 4cef37 > jmp * ;failed anyway + +37f2 : 4c0004 jmp start ;catastrophic error - cannot continue + +37f5 : break2 ;BRK pass 2 +37f5 : e0ad cpx #$ff-'R' + trap_ne +37f7 : d0fe > bne * ;failed not equal (non zero) + +37f9 : c0b1 cpy #$ff-'K'-3 + trap_ne +37fb : d0fe > bne * ;failed not equal (non zero) + +37fd : 850a sta irq_a ;save registers during break test +37ff : 860b stx irq_x +3801 : ba tsx ;test break on stack +3802 : bd0201 lda $102,x + cmp_flag $ff ;break test should have B=1 +3805 : c9ff > cmp #($ff |fao)&m8 ;expected flags + always on bits + + trap_ne ; - no break flag on stack +3807 : d0fe > bne * ;failed not equal (non zero) + +3809 : 68 pla +380a : 0908 ora #decmode ;ignore decmode cleared if 65c02 + cmp_flag $ff ;actual passed flags +380c : c9ff > cmp #($ff |fao)&m8 ;expected flags + always on bits + + trap_ne +380e : d0fe > bne * ;failed not equal (non zero) + +3810 : ba tsx +3811 : e0fc cpx #$fc ;sp -3? (return addr, flags) + trap_ne +3813 : d0fe > bne * ;failed not equal (non zero) + +3815 : adff01 lda $1ff ;propper return on stack +3818 : c909 cmp #hi(brk_ret1) + trap_ne +381a : d0fe > bne * ;failed not equal (non zero) + +381c : adfe01 lda $1fe +381f : c9f7 cmp #lo(brk_ret1) + trap_ne +3821 : d0fe > bne * ;failed not equal (non zero) + + load_flag intdis +3823 : a904 > lda #intdis ;allow test to change I-flag (no mask) + +3825 : 48 pha +3826 : a60b ldx irq_x +3828 : e8 inx ;return registers with modifications +3829 : a50a lda irq_a +382b : 49aa eor #$aa +382d : 28 plp ;N=0, V=0, Z=0, C=0 but original flags should be restored +382e : 40 rti + trap ;runover protection +382f : 4c2f38 > jmp * ;failed anyway + +3832 : 4c0004 jmp start ;catastrophic error - cannot continue + + if report = 1 + include "report.i65" + endif + + ;copy of data to initialize BSS segment + if load_data_direct != 1 + zp_init + zp1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR + zp7f_ db $7f ;test pattern for compare + ;logical zeropage operands + zpOR_ db 0,$1f,$71,$80 ;test pattern for OR + zpAN_ db $0f,$ff,$7f,$80 ;test pattern for AND + zpEO_ db $ff,$0f,$8f,$8f ;test pattern for EOR + ;indirect addressing pointers + ind1_ dw abs1 ;indirect pointer to pattern in absolute memory + dw abs1+1 + dw abs1+2 + dw abs1+3 + dw abs7f + inw1_ dw abs1-$f8 ;indirect pointer for wrap-test pattern + indt_ dw abst ;indirect pointer to store area in absolute memory + dw abst+1 + dw abst+2 + dw abst+3 + inwt_ dw abst-$f8 ;indirect pointer for wrap-test store + indAN_ dw absAN ;indirect pointer to AND pattern in absolute memory + dw absAN+1 + dw absAN+2 + dw absAN+3 + indEO_ dw absEO ;indirect pointer to EOR pattern in absolute memory + dw absEO+1 + dw absEO+2 + dw absEO+3 + indOR_ dw absOR ;indirect pointer to OR pattern in absolute memory + dw absOR+1 + dw absOR+2 + dw absOR+3 + ;add/subtract indirect pointers + adi2_ dw ada2 ;indirect pointer to operand 2 in absolute memory + sbi2_ dw sba2 ;indirect pointer to complemented operand 2 (SBC) + adiy2_ dw ada2-$ff ;with offset for indirect indexed + sbiy2_ dw sba2-$ff + zp_end + if (zp_end - zp_init) != (zp_bss_end - zp_bss) + ;force assembler error if size is different + ERROR ERROR ERROR ;mismatch between bss and zeropage data + endif + data_init + ex_and_ and #0 ;execute immediate opcodes + rts + ex_eor_ eor #0 ;execute immediate opcodes + rts + ex_ora_ ora #0 ;execute immediate opcodes + rts + ex_adc_ adc #0 ;execute immediate opcodes + rts + ex_sbc_ sbc #0 ;execute immediate opcodes + rts + abs1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR + abs7f_ db $7f ;test pattern for compare + ;loads + fLDx_ db fn,fn,0,fz ;expected flags for load + ;shifts + rASL_ ;expected result ASL & ROL -carry + rROL_ db $86,$04,$82,0 ; " + rROLc_ db $87,$05,$83,1 ;expected result ROL +carry + rLSR_ ;expected result LSR & ROR -carry + rROR_ db $61,$41,$20,0 ; " + rRORc_ db $e1,$c1,$a0,$80 ;expected result ROR +carry + fASL_ ;expected flags for shifts + fROL_ db fnc,fc,fn,fz ;no carry in + fROLc_ db fnc,fc,fn,0 ;carry in + fLSR_ + fROR_ db fc,0,fc,fz ;no carry in + fRORc_ db fnc,fn,fnc,fn ;carry in + ;increments (decrements) + rINC_ db $7f,$80,$ff,0,1 ;expected result for INC/DEC + fINC_ db 0,fn,fn,fz,0 ;expected flags for INC/DEC + ;logical memory operand + absOR_ db 0,$1f,$71,$80 ;test pattern for OR + absAN_ db $0f,$ff,$7f,$80 ;test pattern for AND + absEO_ db $ff,$0f,$8f,$8f ;test pattern for EOR + ;logical accu operand + absORa_ db 0,$f1,$1f,0 ;test pattern for OR + absANa_ db $f0,$ff,$ff,$ff ;test pattern for AND + absEOa_ db $ff,$f0,$f0,$0f ;test pattern for EOR + ;logical results + absrlo_ db 0,$ff,$7f,$80 + absflo_ db fz,fn,0,fn + data_end + if (data_end - data_init) != (data_bss_end - data_bss) + ;force assembler error if size is different + ERROR ERROR ERROR ;mismatch between bss and data + endif + + vec_init + dw nmi_trap + dw res_trap + dw irq_trap + vec_bss equ $fffa + endif ;end of RAM init data + + if (load_data_direct = 1) & (ROM_vectors = 1) +fffa = org $fffa ;vectors +fffa : 9d37 dw nmi_trap +fffc : a337 dw res_trap +fffe : ab37 dw irq_trap + endif + +fffa = end start + +No errors in pass 2. +Wrote binary from address $0000 through $ffff. +Total size 65536 bytes. +Program start address is at $0400 (1024). + \ No newline at end of file diff --git a/65c02.ts b/65c02.ts index fb8f050..9805d50 100644 --- a/65c02.ts +++ b/65c02.ts @@ -191,7 +191,7 @@ export default class The65c02 { /** push stuff onto stack */ push(val: number) { if (this.stackPointer.num() >= 0xFF) - throw 'stack overflow (no, not like the website)'; + console.error('stack overflow (no, not like the website)'); this.stackPointer.increment(); this.io.address.set(0x01FF - this.stackPointer.num()); this.io.data.set(val); @@ -199,7 +199,7 @@ export default class The65c02 { } pop(): number { if (this.stackPointer.num() <= 0) - throw 'stack underflow'; + console.error('stack underflow'); this.io.address.set(0x01FF - this.stackPointer.num()); this.read() this.stackPointer.decrement(); diff --git a/README.md b/README.md index 37c870a..0d0acd2 100644 --- a/README.md +++ b/README.md @@ -29,4 +29,8 @@ commands: - `r[ADR]` - breakpoint - `g[ADR]` - goto, change PC - `I[INS]` - breakpoint instruction - \ No newline at end of file + +# known issues + + - supposedly this has some issues with relative addressing + - wozmon BRK's on RETURN, possibly related to the aforementioned relative addressing issues diff --git a/eater.ts b/eater.ts index 4440635..20af12a 100644 --- a/eater.ts +++ b/eater.ts @@ -1,5 +1,6 @@ // deno-lint-ignore-file no-process-globals import The65c02 from "./65c02.ts"; +import matrix from "./opcode_matrix.json" with { type: "json" }; // eater.ts // a runtime meant to mimic ben eater's 65c02 computer @@ -71,6 +72,16 @@ const clock = setInterval(() => { } if(cpu.io.interruptRequest.high && !cpu.IRQBDisable) cpu.io.interruptRequest.LO(); + const instId = ram[cpu.programCounter.num()] + .toString(16) + .padStart(2, '0'); + const goog = (matrix as Record<string, { mnemonic: string, mode: string }>)[instId]; + if (!goog) { + console.log('uh', instId, 'unknown') + throw 'oh no'; + } + const instr = goog; + console.debug(cpu.programCounter.num().toString(16).padStart(4, '0'),instr.mnemonic, instr.mode) cpu.cycle(); // 1MHz i think -}, 1) +}, 100) diff --git a/functional-test.s b/functional-test.s new file mode 100644 index 0000000..dc71882 --- /dev/null +++ b/functional-test.s @@ -0,0 +1,6109 @@ +; +; 6 5 0 2 F U N C T I O N A L T E S T +; +; Copyright (C) 2012-2020 Klaus Dormann +; +; This program is free software: you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation, either version 3 of the License, or +; (at your option) any later version. +; +; This program is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program. If not, see <http://www.gnu.org/licenses/>. + + +; This program is designed to test all opcodes of a 6502 emulator using all +; addressing modes with focus on proper setting of the processor status +; register bits. +; +; version 05-jan-2020 +; contact info at http://2m5.de or email [email protected] +; +; assembled with AS65 written by Frank A. Kingswood +; The assembler as65_142.zip can be obtained from my GitHub repository +; command line switches: -l -m -s2 -w -h0 +; | | | | no page headers in listing +; | | | wide listing (133 char/col) +; | | write intel hex file instead of binary +; | expand macros in listing +; generate pass2 listing +; +; No IO - should be run from a monitor with access to registers. +; To run load intel hex image with a load command, than alter PC to 400 hex +; (code_segment) and enter a go command. +; Loop on program counter determines error or successful completion of test. +; Check listing for relevant traps (jump/branch *). +; Please note that in early tests some instructions will have to be used before +; they are actually tested! +; +; RESET, NMI or IRQ should not occur and will be trapped if vectors are enabled. +; Tests documented behavior of the original NMOS 6502 only! No unofficial +; opcodes. Additional opcodes of newer versions of the CPU (65C02, 65816) will +; not be tested. Decimal ops will only be tested with valid BCD operands and +; N V Z flags will be ignored. +; +; Debugging hints: +; Most of the code is written sequentially. if you hit a trap, check the +; immediately preceding code for the instruction to be tested. Results are +; tested first, flags are checked second by pushing them onto the stack and +; pulling them to the accumulator after the result was checked. The "real" +; flags are no longer valid for the tested instruction at this time! +; If the tested instruction was indexed, the relevant index (X or Y) must +; also be checked. Opposed to the flags, X and Y registers are still valid. +; +; versions: +; 28-jul-2012 1st version distributed for testing +; 29-jul-2012 fixed references to location 0, now #0 +; added license - GPLv3 +; 30-jul-2012 added configuration options +; 01-aug-2012 added trap macro to allow user to change error handling +; 01-dec-2012 fixed trap in branch field must be a branch +; 02-mar-2013 fixed PLA flags not tested +; 19-jul-2013 allowed ROM vectors to be loaded when load_data_direct = 0 +; added test sequence check to detect if tests jump their fence +; 23-jul-2013 added RAM integrity check option +; 16-aug-2013 added error report to standard output option +; 13-dec-2014 added binary/decimal opcode table switch test +; 14-dec-2014 improved relative address test +; 23-aug-2015 added option to disable self modifying tests +; 24-aug-2015 all self modifying immediate opcodes now execute in data RAM +; added small branch offset pretest +; 21-oct-2015 added option to disable decimal mode ADC & SBC tests +; 04-dec-2017 fixed BRK only tested with interrupts enabled +; added option to skip the remainder of a failing test +; in report.i65 +; 05-jan-2020 fixed shifts not testing zero result and flag when last 1-bit +; is shifted out + +; C O N F I G U R A T I O N + +;ROM_vectors writable (0=no, 1=yes) +;if ROM vectors can not be used interrupts will not be trapped +;as a consequence BRK can not be tested but will be emulated to test RTI +ROM_vectors = 1 + +;load_data_direct (0=move from code segment, 1=load directly) +;loading directly is preferred but may not be supported by your platform +;0 produces only consecutive object code, 1 is not suitable for a binary image +load_data_direct = 1 + +;I_flag behavior (0=force enabled, 1=force disabled, 2=prohibit change, 3=allow +;change) 2 requires extra code and is not recommended. SEI & CLI can only be +;tested if you allow changing the interrupt status (I_flag = 3) +I_flag = 3 + +;configure memory - try to stay away from memory used by the system +;zero_page memory start address, $52 (82) consecutive Bytes required +; add 2 if I_flag = 2 +zero_page = $a + +;data_segment memory start address, $7B (123) consecutive Bytes required +data_segment = $200 + if (data_segment & $ff) != 0 + ERROR ERROR ERROR low byte of data_segment MUST be $00 !! + endif + +;code_segment memory start address, 13.1kB of consecutive space required +; add 2.5 kB if I_flag = 2 +code_segment = $400 + +;self modifying code may be disabled to allow running in ROM +;0=part of the code is self modifying and must reside in RAM +;1=tests disabled: branch range +disable_selfmod = 0 + +;report errors through I/O channel (0=use standard self trap loops, 1=include +;report.i65 as I/O channel, add 3.5 kB) +report = 0 + +;RAM integrity test option. Checks for undesired RAM writes. +;set lowest non RAM or RAM mirror address page (-1=disable, 0=64k, $40=16k) +;leave disabled if a monitor, OS or background interrupt is allowed to alter RAM +ram_top = -1 + +;disable test decimal mode ADC & SBC, 0=enable, 1=disable, +;2=disable including decimal flag in processor status +disable_decimal = 0 + + noopt ;do not take shortcuts + +;macros for error & success traps to allow user modification +;example: +;trap macro +; jsr my_error_handler +; endm +;trap_eq macro +; bne skip\? +; trap ;failed equal (zero) +;skip\? +; endm +; +; my_error_handler should pop the calling address from the stack and report it. +; putting larger portions of code (more than 3 bytes) inside the trap macro +; may lead to branch range problems for some tests. + if report = 0 +trap macro + jmp * ;failed anyway + endm +trap_eq macro + beq * ;failed equal (zero) + endm +trap_ne macro + bne * ;failed not equal (non zero) + endm +trap_cs macro + bcs * ;failed carry set + endm +trap_cc macro + bcc * ;failed carry clear + endm +trap_mi macro + bmi * ;failed minus (bit 7 set) + endm +trap_pl macro + bpl * ;failed plus (bit 7 clear) + endm +trap_vs macro + bvs * ;failed overflow set + endm +trap_vc macro + bvc * ;failed overflow clear + endm +; please observe that during the test the stack gets invalidated +; therefore a RTS inside the success macro is not possible +success macro + jmp * ;test passed, no errors + endm + endif + if report = 1 +trap macro + jsr report_error + endm +trap_eq macro + bne skip\? + trap ;failed equal (zero) +skip\? + endm +trap_ne macro + beq skip\? + trap ;failed not equal (non zero) +skip\? + endm +trap_cs macro + bcc skip\? + trap ;failed carry set +skip\? + endm +trap_cc macro + bcs skip\? + trap ;failed carry clear +skip\? + endm +trap_mi macro + bpl skip\? + trap ;failed minus (bit 7 set) +skip\? + endm +trap_pl macro + bmi skip\? + trap ;failed plus (bit 7 clear) +skip\? + endm +trap_vs macro + bvc skip\? + trap ;failed overflow set +skip\? + endm +trap_vc macro + bvs skip\? + trap ;failed overflow clear +skip\? + endm +; please observe that during the test the stack gets invalidated +; therefore a RTS inside the success macro is not possible +success macro + jsr report_success + endm + endif + + +carry equ %00000001 ;flag bits in status +zero equ %00000010 +intdis equ %00000100 +decmode equ %00001000 +break equ %00010000 +reserv equ %00100000 +overfl equ %01000000 +minus equ %10000000 + +fc equ carry +fz equ zero +fzc equ carry+zero +fv equ overfl +fvz equ overfl+zero +fn equ minus +fnc equ minus+carry +fnz equ minus+zero +fnzc equ minus+zero+carry +fnv equ minus+overfl + +fao equ break+reserv ;bits always on after PHP, BRK +fai equ fao+intdis ;+ forced interrupt disable +faod equ fao+decmode ;+ ignore decimal +faid equ fai+decmode ;+ ignore decimal +m8 equ $ff ;8 bit mask +m8i equ $ff&~intdis ;8 bit mask - interrupt disable + +;macros to allow masking of status bits. +;masking test of decimal bit +;masking of interrupt enable/disable on load and compare +;masking of always on bits after PHP or BRK (unused & break) on compare + if disable_decimal < 2 + if I_flag = 0 +load_flag macro + lda #\1&m8i ;force enable interrupts (mask I) + endm +cmp_flag macro + cmp #(\1|fao)&m8i ;I_flag is always enabled + always on bits + endm +eor_flag macro + eor #(\1&m8i|fao) ;mask I, invert expected flags + always on bits + endm + endif + if I_flag = 1 +load_flag macro + lda #\1|intdis ;force disable interrupts + endm +cmp_flag macro + cmp #(\1|fai)&m8 ;I_flag is always disabled + always on bits + endm +eor_flag macro + eor #(\1|fai) ;invert expected flags + always on bits + I + endm + endif + if I_flag = 2 +load_flag macro + lda #\1 + ora flag_I_on ;restore I-flag + and flag_I_off + endm +cmp_flag macro + eor flag_I_on ;I_flag is never changed + cmp #(\1|fao)&m8i ;expected flags + always on bits, mask I + endm +eor_flag macro + eor flag_I_on ;I_flag is never changed + eor #(\1&m8i|fao) ;mask I, invert expected flags + always on bits + endm + endif + if I_flag = 3 +load_flag macro + lda #\1 ;allow test to change I-flag (no mask) + endm +cmp_flag macro + cmp #(\1|fao)&m8 ;expected flags + always on bits + endm +eor_flag macro + eor #\1|fao ;invert expected flags + always on bits + endm + endif + else + if I_flag = 0 +load_flag macro + lda #\1&m8i ;force enable interrupts (mask I) + endm +cmp_flag macro + ora #decmode ;ignore decimal mode bit + cmp #(\1|faod)&m8i ;I_flag is always enabled + always on bits + endm +eor_flag macro + ora #decmode ;ignore decimal mode bit + eor #(\1&m8i|faod) ;mask I, invert expected flags + always on bits + endm + endif + if I_flag = 1 +load_flag macro + lda #\1|intdis ;force disable interrupts + endm +cmp_flag macro + ora #decmode ;ignore decimal mode bit + cmp #(\1|faid)&m8 ;I_flag is always disabled + always on bits + endm +eor_flag macro + ora #decmode ;ignore decimal mode bit + eor #(\1|faid) ;invert expected flags + always on bits + I + endm + endif + if I_flag = 2 +load_flag macro + lda #\1 + ora flag_I_on ;restore I-flag + and flag_I_off + endm +cmp_flag macro + eor flag_I_on ;I_flag is never changed + ora #decmode ;ignore decimal mode bit + cmp #(\1|faod)&m8i ;expected flags + always on bits, mask I + endm +eor_flag macro + eor flag_I_on ;I_flag is never changed + ora #decmode ;ignore decimal mode bit + eor #(\1&m8i|faod) ;mask I, invert expected flags + always on bits + endm + endif + if I_flag = 3 +load_flag macro + lda #\1 ;allow test to change I-flag (no mask) + endm +cmp_flag macro + ora #decmode ;ignore decimal mode bit + cmp #(\1|faod)&m8 ;expected flags + always on bits + endm +eor_flag macro + ora #decmode ;ignore decimal mode bit + eor #\1|faod ;invert expected flags + always on bits + endm + endif + endif + +;macros to set (register|memory|zeropage) & status +set_stat macro ;setting flags in the processor status register + load_flag \1 + pha ;use stack to load status + plp + endm + +set_a macro ;precharging accu & status + load_flag \2 + pha ;use stack to load status + lda #\1 ;precharge accu + plp + endm + +set_x macro ;precharging index & status + load_flag \2 + pha ;use stack to load status + ldx #\1 ;precharge index x + plp + endm + +set_y macro ;precharging index & status + load_flag \2 + pha ;use stack to load status + ldy #\1 ;precharge index y + plp + endm + +set_ax macro ;precharging indexed accu & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;precharge accu + plp + endm + +set_ay macro ;precharging indexed accu & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,y ;precharge accu + plp + endm + +set_z macro ;precharging indexed zp & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to zeropage + sta zpt + plp + endm + +set_zx macro ;precharging zp,x & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to indexed zeropage + sta zpt,x + plp + endm + +set_abs macro ;precharging indexed memory & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to memory + sta abst + plp + endm + +set_absx macro ;precharging abs,x & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to indexed memory + sta abst,x + plp + endm + +;macros to test (register|memory|zeropage) & status & (mask) +tst_stat macro ;testing flags in the processor status register + php ;save status + pla ;use stack to retrieve status + pha + cmp_flag \1 + trap_ne + plp ;restore status + endm + +tst_a macro ;testing result in accu & flags + php ;save flags + cmp #\1 ;test result + trap_ne + pla ;load status + pha + cmp_flag \2 + trap_ne + plp ;restore status + endm + +tst_x macro ;testing result in x index & flags + php ;save flags + cpx #\1 ;test result + trap_ne + pla ;load status + pha + cmp_flag \2 + trap_ne + plp ;restore status + endm + +tst_y macro ;testing result in y index & flags + php ;save flags + cpy #\1 ;test result + trap_ne + pla ;load status + pha + cmp_flag \2 + trap_ne + plp ;restore status + endm + +tst_ax macro ;indexed testing result in accu & flags + php ;save flags + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne ; + endm + +tst_ay macro ;indexed testing result in accu & flags + php ;save flags + cmp \1,y ;test result + trap_ne ; + pla ;load status + eor_flag \3 + cmp \2,y ;test flags + trap_ne + endm + +tst_z macro ;indexed testing result in zp & flags + php ;save flags + lda zpt + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + +tst_zx macro ;testing result in zp,x & flags + php ;save flags + lda zpt,x + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + +tst_abs macro ;indexed testing result in memory & flags + php ;save flags + lda abst + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + +tst_absx macro ;testing result in abs,x & flags + php ;save flags + lda abst,x + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + +; RAM integrity test +; verifies that none of the previous tests has altered RAM outside of the +; designated write areas. +; uses zpt word as indirect pointer, zpt+2 word as checksum + if ram_top > -1 +check_ram macro + cld + lda #0 + sta zpt ;set low byte of indirect pointer + sta zpt+3 ;checksum high byte + if disable_selfmod = 0 + sta range_adr ;reset self modifying code + endif + clc + ldx #zp_bss-zero_page ;zeropage - write test area +ccs3\? adc zero_page,x + bcc ccs2\? + inc zpt+3 ;carry to high byte + clc +ccs2\? inx + bne ccs3\? + ldx #hi(abs1) ;set high byte of indirect pointer + stx zpt+1 + ldy #lo(abs1) ;data after write & execute test area +ccs5\? adc (zpt),y + bcc ccs4\? + inc zpt+3 ;carry to high byte + clc +ccs4\? iny + bne ccs5\? + inx ;advance RAM high address + stx zpt+1 + cpx #ram_top + bne ccs5\? + sta zpt+2 ;checksum low is + cmp ram_chksm ;checksum low expected + trap_ne ;checksum mismatch + lda zpt+3 ;checksum high is + cmp ram_chksm+1 ;checksum high expected + trap_ne ;checksum mismatch + endm + else +check_ram macro + ;RAM check disabled - RAM size not set + endm + endif + +next_test macro ;make sure, tests don't jump the fence + lda test_case ;previous test + cmp #test_num + trap_ne ;test is out of sequence +test_num = test_num + 1 + lda #test_num ;*** next tests' number + sta test_case + ;check_ram ;uncomment to find altered RAM after each test + endm + + if load_data_direct = 1 + data + else + bss ;uninitialized segment, copy of data at end of code! + endif + org zero_page +;break test interrupt save +irq_a ds 1 ;a register +irq_x ds 1 ;x register + if I_flag = 2 +;masking for I bit in status +flag_I_on ds 1 ;or mask to load flags +flag_I_off ds 1 ;and mask to load flags + endif +zpt ;6 bytes store/modify test area +;add/subtract operand generation and result/flag prediction +adfc ds 1 ;carry flag before op +ad1 ds 1 ;operand 1 - accumulator +ad2 ds 1 ;operand 2 - memory / immediate +adrl ds 1 ;expected result bits 0-7 +adrh ds 1 ;expected result bit 8 (carry) +adrf ds 1 ;expected flags NV0000ZC (only binary mode) +sb2 ds 1 ;operand 2 complemented for subtract +zp_bss +zps db $80,1 ;additional shift pattern to test zero result & flag +zp1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +zp7f db $7f ;test pattern for compare +;logical zeropage operands +zpOR db 0,$1f,$71,$80 ;test pattern for OR +zpAN db $0f,$ff,$7f,$80 ;test pattern for AND +zpEO db $ff,$0f,$8f,$8f ;test pattern for EOR +;indirect addressing pointers +ind1 dw abs1 ;indirect pointer to pattern in absolute memory + dw abs1+1 + dw abs1+2 + dw abs1+3 + dw abs7f +inw1 dw abs1-$f8 ;indirect pointer for wrap-test pattern +indt dw abst ;indirect pointer to store area in absolute memory + dw abst+1 + dw abst+2 + dw abst+3 +inwt dw abst-$f8 ;indirect pointer for wrap-test store +indAN dw absAN ;indirect pointer to AND pattern in absolute memory + dw absAN+1 + dw absAN+2 + dw absAN+3 +indEO dw absEO ;indirect pointer to EOR pattern in absolute memory + dw absEO+1 + dw absEO+2 + dw absEO+3 +indOR dw absOR ;indirect pointer to OR pattern in absolute memory + dw absOR+1 + dw absOR+2 + dw absOR+3 +;add/subtract indirect pointers +adi2 dw ada2 ;indirect pointer to operand 2 in absolute memory +sbi2 dw sba2 ;indirect pointer to complemented operand 2 (SBC) +adiy2 dw ada2-$ff ;with offset for indirect indexed +sbiy2 dw sba2-$ff +zp_bss_end + + org data_segment +test_case ds 1 ;current test number +ram_chksm ds 2 ;checksum for RAM integrity test +;add/subtract operand copy - abs tests write area +abst ;6 bytes store/modify test area +ada2 ds 1 ;operand 2 +sba2 ds 1 ;operand 2 complemented for subtract + ds 4 ;fill remaining bytes +data_bss + if load_data_direct = 1 +ex_andi and #0 ;execute immediate opcodes + rts +ex_eori eor #0 ;execute immediate opcodes + rts +ex_orai ora #0 ;execute immediate opcodes + rts +ex_adci adc #0 ;execute immediate opcodes + rts +ex_sbci sbc #0 ;execute immediate opcodes + rts + else +ex_andi ds 3 +ex_eori ds 3 +ex_orai ds 3 +ex_adci ds 3 +ex_sbci ds 3 + endif +;zps db $80,1 ;additional shift patterns test zero result & flag +abs1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +abs7f db $7f ;test pattern for compare +;loads +fLDx db fn,fn,0,fz ;expected flags for load +;shifts +rASL ;expected result ASL & ROL -carry +rROL db 0,2,$86,$04,$82,0 +rROLc db 1,3,$87,$05,$83,1 ;expected result ROL +carry +rLSR ;expected result LSR & ROR -carry +rROR db $40,0,$61,$41,$20,0 +rRORc db $c0,$80,$e1,$c1,$a0,$80 ;expected result ROR +carry +fASL ;expected flags for shifts +fROL db fzc,0,fnc,fc,fn,fz ;no carry in +fROLc db fc,0,fnc,fc,fn,0 ;carry in +fLSR +fROR db 0,fzc,fc,0,fc,fz ;no carry in +fRORc db fn,fnc,fnc,fn,fnc,fn ;carry in +;increments (decrements) +rINC db $7f,$80,$ff,0,1 ;expected result for INC/DEC +fINC db 0,fn,fn,fz,0 ;expected flags for INC/DEC +;logical memory operand +absOR db 0,$1f,$71,$80 ;test pattern for OR +absAN db $0f,$ff,$7f,$80 ;test pattern for AND +absEO db $ff,$0f,$8f,$8f ;test pattern for EOR +;logical accu operand +absORa db 0,$f1,$1f,0 ;test pattern for OR +absANa db $f0,$ff,$ff,$ff ;test pattern for AND +absEOa db $ff,$f0,$f0,$0f ;test pattern for EOR +;logical results +absrlo db 0,$ff,$7f,$80 +absflo db fz,fn,0,fn +data_bss_end + + + code + org code_segment +start cld + ldx #$ff + txs + lda #0 ;*** test 0 = initialize + sta test_case +test_num = 0 + +;stop interrupts before initializing BSS + if I_flag = 1 + sei + endif + +;initialize I/O for report channel + if report = 1 + jsr report_init + endif + +;pretest small branch offset + ldx #5 + jmp psb_test +psb_bwok + ldy #5 + bne psb_forw + trap ;branch should be taken + dey ;forward landing zone + dey + dey + dey + dey +psb_forw + dey + dey + dey + dey + dey + beq psb_fwok + trap ;forward offset + + dex ;backward landing zone + dex + dex + dex + dex +psb_back + dex + dex + dex + dex + dex + beq psb_bwok + trap ;backward offset +psb_test + bne psb_back + trap ;branch should be taken +psb_fwok + +;initialize BSS segment + if load_data_direct != 1 + ldx #zp_end-zp_init-1 +ld_zp lda zp_init,x + sta zp_bss,x + dex + bpl ld_zp + ldx #data_end-data_init-1 +ld_data lda data_init,x + sta data_bss,x + dex + bpl ld_data + if ROM_vectors = 1 + ldx #5 +ld_vect lda vec_init,x + sta vec_bss,x + dex + bpl ld_vect + endif + endif + +;retain status of interrupt flag + if I_flag = 2 + php + pla + and #4 ;isolate flag + sta flag_I_on ;or mask + eor #lo(~4) ;reverse + sta flag_I_off ;and mask + endif + +;generate checksum for RAM integrity test + if ram_top > -1 + lda #0 + sta zpt ;set low byte of indirect pointer + sta ram_chksm+1 ;checksum high byte + if disable_selfmod = 0 + sta range_adr ;reset self modifying code + endif + clc + ldx #zp_bss-zero_page ;zeropage - write test area +gcs3 adc zero_page,x + bcc gcs2 + inc ram_chksm+1 ;carry to high byte + clc +gcs2 inx + bne gcs3 + ldx #hi(abs1) ;set high byte of indirect pointer + stx zpt+1 + ldy #lo(abs1) ;data after write & execute test area +gcs5 adc (zpt),y + bcc gcs4 + inc ram_chksm+1 ;carry to high byte + clc +gcs4 iny + bne gcs5 + inx ;advance RAM high address + stx zpt+1 + cpx #ram_top + bne gcs5 + sta ram_chksm ;checksum complete + endif + next_test + + if disable_selfmod = 0 +;testing relative addressing with BEQ + ldy #$fe ;testing maximum range, not -1/-2 (invalid/self adr) +range_loop + dey ;next relative address + tya + tax ;precharge count to end of loop + bpl range_fw ;calculate relative address + clc ;avoid branch self or to relative address of branch + adc #2 + nop ;offset landing zone - tolerate +/-5 offset to branch + nop + nop + nop + nop +range_fw + nop + nop + nop + nop + nop + eor #$7f ;complement except sign + sta range_adr ;load into test target + lda #0 ;should set zero flag in status register + jmp range_op + + dex ; offset landing zone - backward branch too far + dex + dex + dex + dex + ;relative address target field with branch under test in the middle + dex ;-128 - max backward + dex + dex + dex + dex + dex + dex + dex + dex ;-120 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-110 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-100 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-90 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-80 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-70 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-60 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-50 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-40 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-30 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-20 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-10 + dex + dex + dex + dex + dex + dex + dex ;-3 +range_op ;test target with zero flag=0, z=1 if previous dex +range_adr = *+1 ;modifiable relative address + beq *+64 ;+64 if called without modification + dex ;+0 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+10 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+20 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+30 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+40 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+50 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+60 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+70 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+80 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+90 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+100 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+110 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+120 + dex + dex + dex + dex + dex + dex + nop ;offset landing zone - forward branch too far + nop + nop + nop + nop + beq range_ok ;+127 - max forward + trap ; bad range + nop ;offset landing zone - tolerate +/-5 offset to branch + nop + nop + nop + nop +range_ok + nop + nop + nop + nop + nop + cpy #0 + beq range_end + jmp range_loop +range_end ;range test successful + endif + next_test + +;partial test BNE & CMP, CPX, CPY immediate + cpy #1 ;testing BNE true + bne test_bne + trap +test_bne + lda #0 + cmp #0 ;test compare immediate + trap_ne + trap_cc + trap_mi + cmp #1 + trap_eq + trap_cs + trap_pl + tax + cpx #0 ;test compare x immediate + trap_ne + trap_cc + trap_mi + cpx #1 + trap_eq + trap_cs + trap_pl + tay + cpy #0 ;test compare y immediate + trap_ne + trap_cc + trap_mi + cpy #1 + trap_eq + trap_cs + trap_pl + next_test +;testing stack operations PHA PHP PLA PLP + + ldx #$ff ;initialize stack + txs + lda #$55 + pha + lda #$aa + pha + cmp $1fe ;on stack ? + trap_ne + tsx + txa ;overwrite accu + cmp #$fd ;sp decremented? + trap_ne + pla + cmp #$aa ;successful retreived from stack? + trap_ne + pla + cmp #$55 + trap_ne + cmp $1ff ;remains on stack? + trap_ne + tsx + cpx #$ff ;sp incremented? + trap_ne + next_test + +;testing branch decisions BPL BMI BVC BVS BCC BCS BNE BEQ + set_stat $ff ;all on + bpl nbr1 ;branches should not be taken + bvc nbr2 + bcc nbr3 + bne nbr4 + bmi br1 ;branches should be taken + trap +br1 bvs br2 + trap +br2 bcs br3 + trap +br3 beq br4 + trap +nbr1 + trap ;previous bpl taken +nbr2 + trap ;previous bvc taken +nbr3 + trap ;previous bcc taken +nbr4 + trap ;previous bne taken +br4 php + tsx + cpx #$fe ;sp after php? + trap_ne + pla + cmp_flag $ff ;returned all flags on? + trap_ne + tsx + cpx #$ff ;sp after php? + trap_ne + set_stat 0 ;all off + bmi nbr11 ;branches should not be taken + bvs nbr12 + bcs nbr13 + beq nbr14 + bpl br11 ;branches should be taken + trap +br11 bvc br12 + trap +br12 bcc br13 + trap +br13 bne br14 + trap +nbr11 + trap ;previous bmi taken +nbr12 + trap ;previous bvs taken +nbr13 + trap ;previous bcs taken +nbr14 + trap ;previous beq taken +br14 php + pla + cmp_flag 0 ;flags off except break (pushed by sw) + reserved? + trap_ne + ;crosscheck flags + set_stat zero + bne brzs1 + beq brzs2 +brzs1 + trap ;branch zero/non zero +brzs2 bcs brzs3 + bcc brzs4 +brzs3 + trap ;branch carry/no carry +brzs4 bmi brzs5 + bpl brzs6 +brzs5 + trap ;branch minus/plus +brzs6 bvs brzs7 + bvc brzs8 +brzs7 + trap ;branch overflow/no overflow +brzs8 + set_stat carry + beq brcs1 + bne brcs2 +brcs1 + trap ;branch zero/non zero +brcs2 bcc brcs3 + bcs brcs4 +brcs3 + trap ;branch carry/no carry +brcs4 bmi brcs5 + bpl brcs6 +brcs5 + trap ;branch minus/plus +brcs6 bvs brcs7 + bvc brcs8 +brcs7 + trap ;branch overflow/no overflow + +brcs8 + set_stat minus + beq brmi1 + bne brmi2 +brmi1 + trap ;branch zero/non zero +brmi2 bcs brmi3 + bcc brmi4 +brmi3 + trap ;branch carry/no carry +brmi4 bpl brmi5 + bmi brmi6 +brmi5 + trap ;branch minus/plus +brmi6 bvs brmi7 + bvc brmi8 +brmi7 + trap ;branch overflow/no overflow +brmi8 + set_stat overfl + beq brvs1 + bne brvs2 +brvs1 + trap ;branch zero/non zero +brvs2 bcs brvs3 + bcc brvs4 +brvs3 + trap ;branch carry/no carry +brvs4 bmi brvs5 + bpl brvs6 +brvs5 + trap ;branch minus/plus +brvs6 bvc brvs7 + bvs brvs8 +brvs7 + trap ;branch overflow/no overflow +brvs8 + set_stat $ff-zero + beq brzc1 + bne brzc2 +brzc1 + trap ;branch zero/non zero +brzc2 bcc brzc3 + bcs brzc4 +brzc3 + trap ;branch carry/no carry +brzc4 bpl brzc5 + bmi brzc6 +brzc5 + trap ;branch minus/plus +brzc6 bvc brzc7 + bvs brzc8 +brzc7 + trap ;branch overflow/no overflow +brzc8 + set_stat $ff-carry + bne brcc1 + beq brcc2 +brcc1 + trap ;branch zero/non zero +brcc2 bcs brcc3 + bcc brcc4 +brcc3 + trap ;branch carry/no carry +brcc4 bpl brcc5 + bmi brcc6 +brcc5 + trap ;branch minus/plus +brcc6 bvc brcc7 + bvs brcc8 +brcc7 + trap ;branch overflow/no overflow +brcc8 + set_stat $ff-minus + bne brpl1 + beq brpl2 +brpl1 + trap ;branch zero/non zero +brpl2 bcc brpl3 + bcs brpl4 +brpl3 + trap ;branch carry/no carry +brpl4 bmi brpl5 + bpl brpl6 +brpl5 + trap ;branch minus/plus +brpl6 bvc brpl7 + bvs brpl8 +brpl7 + trap ;branch overflow/no overflow +brpl8 + set_stat $ff-overfl + bne brvc1 + beq brvc2 +brvc1 + trap ;branch zero/non zero +brvc2 bcc brvc3 + bcs brvc4 +brvc3 + trap ;branch carry/no carry +brvc4 bpl brvc5 + bmi brvc6 +brvc5 + trap ;branch minus/plus +brvc6 bvs brvc7 + bvc brvc8 +brvc7 + trap ;branch overflow/no overflow +brvc8 + next_test + +; test PHA does not alter flags or accumulator but PLA does + ldx #$55 ;x & y protected + ldy #$aa + set_a 1,$ff ;push + pha + tst_a 1,$ff + set_a 0,0 + pha + tst_a 0,0 + set_a $ff,$ff + pha + tst_a $ff,$ff + set_a 1,0 + pha + tst_a 1,0 + set_a 0,$ff + pha + tst_a 0,$ff + set_a $ff,0 + pha + tst_a $ff,0 + set_a 0,$ff ;pull + pla + tst_a $ff,$ff-zero + set_a $ff,0 + pla + tst_a 0,zero + set_a $fe,$ff + pla + tst_a 1,$ff-zero-minus + set_a 0,0 + pla + tst_a $ff,minus + set_a $ff,$ff + pla + tst_a 0,$ff-minus + set_a $fe,0 + pla + tst_a 1,0 + cpx #$55 ;x & y unchanged? + trap_ne + cpy #$aa + trap_ne + next_test + +; partial pretest EOR # + set_a $3c,0 + eor #$c3 + tst_a $ff,fn + set_a $c3,0 + eor #$c3 + tst_a 0,fz + next_test + +; PC modifying instructions except branches (NOP, JMP, JSR, RTS, BRK, RTI) +; testing NOP + ldx #$24 + ldy #$42 + set_a $18,0 + nop + tst_a $18,0 + cpx #$24 + trap_ne + cpy #$42 + trap_ne + ldx #$db + ldy #$bd + set_a $e7,$ff + nop + tst_a $e7,$ff + cpx #$db + trap_ne + cpy #$bd + trap_ne + next_test + +; jump absolute + set_stat $0 + lda #'F' + ldx #'A' + ldy #'R' ;N=0, V=0, Z=0, C=0 + jmp test_far + nop + nop + trap_ne ;runover protection + inx + inx +far_ret + trap_eq ;returned flags OK? + trap_pl + trap_cc + trap_vc + cmp #('F'^$aa) ;returned registers OK? + trap_ne + cpx #('A'+1) + trap_ne + cpy #('R'-3) + trap_ne + dex + iny + iny + iny + eor #$aa ;N=0, V=1, Z=0, C=1 + jmp test_near + nop + nop + trap_ne ;runover protection + inx + inx +test_near + trap_eq ;passed flags OK? + trap_mi + trap_cc + trap_vc + cmp #'F' ;passed registers OK? + trap_ne + cpx #'A' + trap_ne + cpy #'R' + trap_ne + next_test + +; jump indirect + set_stat 0 + lda #'I' + ldx #'N' + ldy #'D' ;N=0, V=0, Z=0, C=0 + jmp (ptr_tst_ind) + nop + trap_ne ;runover protection + dey + dey +ind_ret + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_eq ;returned flags OK? + trap_pl + trap_cc + trap_vc + cmp #('I'^$aa) ;returned registers OK? + trap_ne + cpx #('N'+1) + trap_ne + cpy #('D'-6) + trap_ne + tsx ;SP check + cpx #$ff + trap_ne + next_test + +; jump subroutine & return from subroutine + set_stat 0 + lda #'J' + ldx #'S' + ldy #'R' ;N=0, V=0, Z=0, C=0 + jsr test_jsr +jsr_ret = *-1 ;last address of jsr = return address + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_eq ;returned flags OK? + trap_pl + trap_cc + trap_vc + cmp #('J'^$aa) ;returned registers OK? + trap_ne + cpx #('S'+1) + trap_ne + cpy #('R'-6) + trap_ne + tsx ;sp? + cpx #$ff + trap_ne + next_test + +; break & return from interrupt + if ROM_vectors = 1 + load_flag 0 ;with interrupts enabled if allowed! + pha + lda #'B' + ldx #'R' + ldy #'K' + plp ;N=0, V=0, Z=0, C=0 + brk + else + lda #hi brk_ret0 ;emulated break + pha + lda #lo brk_ret0 + pha + load_flag fao ;set break & unused on stack + pha + load_flag intdis ;during interrupt + pha + lda #'B' + ldx #'R' + ldy #'K' + plp ;N=0, V=0, Z=0, C=0 + jmp irq_trap + endif + dey ;should not be executed +brk_ret0 ;address of break return + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + cmp #'B'^$aa ;returned registers OK? + ;the IRQ vector was never executed if A & X stay unmodified + trap_ne + cpx #'R'+1 + trap_ne + cpy #'K'-6 + trap_ne + pla ;returned flags OK (unchanged)? + cmp_flag 0 + trap_ne + tsx ;sp? + cpx #$ff + trap_ne + if ROM_vectors = 1 + load_flag $ff ;with interrupts disabled if allowed! + pha + lda #$ff-'B' + ldx #$ff-'R' + ldy #$ff-'K' + plp ;N=1, V=1, Z=1, C=1 + brk + else + lda #hi brk_ret1 ;emulated break + pha + lda #lo brk_ret1 + pha + load_flag $ff + pha ;set break & unused on stack + pha ;actual flags + lda #$ff-'B' + ldx #$ff-'R' + ldy #$ff-'K' + plp ;N=1, V=1, Z=1, C=1 + jmp irq_trap + endif + dey ;should not be executed +brk_ret1 ;address of break return + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + cmp #($ff-'B')^$aa ;returned registers OK? + ;the IRQ vector was never executed if A & X stay unmodified + trap_ne + cpx #$ff-'R'+1 + trap_ne + cpy #$ff-'K'-6 + trap_ne + pla ;returned flags OK (unchanged)? + cmp_flag $ff + trap_ne + tsx ;sp? + cpx #$ff + trap_ne + next_test + +; test set and clear flags CLC CLI CLD CLV SEC SEI SED + set_stat $ff + clc + tst_stat $ff-carry + sec + tst_stat $ff + if I_flag = 3 + cli + tst_stat $ff-intdis + sei + tst_stat $ff + endif + cld + tst_stat $ff-decmode + sed + tst_stat $ff + clv + tst_stat $ff-overfl + set_stat 0 + tst_stat 0 + sec + tst_stat carry + clc + tst_stat 0 + if I_flag = 3 + sei + tst_stat intdis + cli + tst_stat 0 + endif + sed + tst_stat decmode + cld + tst_stat 0 + set_stat overfl + tst_stat overfl + clv + tst_stat 0 + next_test +; testing index register increment/decrement and transfer +; INX INY DEX DEY TAX TXA TAY TYA + ldx #$fe + set_stat $ff + inx ;ff + tst_x $ff,$ff-zero + inx ;00 + tst_x 0,$ff-minus + inx ;01 + tst_x 1,$ff-minus-zero + dex ;00 + tst_x 0,$ff-minus + dex ;ff + tst_x $ff,$ff-zero + dex ;fe + set_stat 0 + inx ;ff + tst_x $ff,minus + inx ;00 + tst_x 0,zero + inx ;01 + tst_x 1,0 + dex ;00 + tst_x 0,zero + dex ;ff + tst_x $ff,minus + + ldy #$fe + set_stat $ff + iny ;ff + tst_y $ff,$ff-zero + iny ;00 + tst_y 0,$ff-minus + iny ;01 + tst_y 1,$ff-minus-zero + dey ;00 + tst_y 0,$ff-minus + dey ;ff + tst_y $ff,$ff-zero + dey ;fe + set_stat 0 + iny ;ff + tst_y $ff,0+minus + iny ;00 + tst_y 0,zero + iny ;01 + tst_y 1,0 + dey ;00 + tst_y 0,zero + dey ;ff + tst_y $ff,minus + + ldx #$ff + set_stat $ff + txa + tst_a $ff,$ff-zero + php + inx ;00 + plp + txa + tst_a 0,$ff-minus + php + inx ;01 + plp + txa + tst_a 1,$ff-minus-zero + set_stat 0 + txa + tst_a 1,0 + php + dex ;00 + plp + txa + tst_a 0,zero + php + dex ;ff + plp + txa + tst_a $ff,minus + + ldy #$ff + set_stat $ff + tya + tst_a $ff,$ff-zero + php + iny ;00 + plp + tya + tst_a 0,$ff-minus + php + iny ;01 + plp + tya + tst_a 1,$ff-minus-zero + set_stat 0 + tya + tst_a 1,0 + php + dey ;00 + plp + tya + tst_a 0,zero + php + dey ;ff + plp + tya + tst_a $ff,minus + + load_flag $ff + pha + ldx #$ff ;ff + txa + plp + tay + tst_y $ff,$ff-zero + php + inx ;00 + txa + plp + tay + tst_y 0,$ff-minus + php + inx ;01 + txa + plp + tay + tst_y 1,$ff-minus-zero + load_flag 0 + pha + lda #0 + txa + plp + tay + tst_y 1,0 + php + dex ;00 + txa + plp + tay + tst_y 0,zero + php + dex ;ff + txa + plp + tay + tst_y $ff,minus + + + load_flag $ff + pha + ldy #$ff ;ff + tya + plp + tax + tst_x $ff,$ff-zero + php + iny ;00 + tya + plp + tax + tst_x 0,$ff-minus + php + iny ;01 + tya + plp + tax + tst_x 1,$ff-minus-zero + load_flag 0 + pha + lda #0 ;preset status + tya + plp + tax + tst_x 1,0 + php + dey ;00 + tya + plp + tax + tst_x 0,zero + php + dey ;ff + tya + plp + tax + tst_x $ff,minus + next_test + +;TSX sets NZ - TXS does not +; This section also tests for proper stack wrap around. + ldx #1 ;01 + set_stat $ff + txs + php + lda $101 + cmp_flag $ff + trap_ne + set_stat 0 + txs + php + lda $101 + cmp_flag 0 + trap_ne + dex ;00 + set_stat $ff + txs + php + lda $100 + cmp_flag $ff + trap_ne + set_stat 0 + txs + php + lda $100 + cmp_flag 0 + trap_ne + dex ;ff + set_stat $ff + txs + php + lda $1ff + cmp_flag $ff + trap_ne + set_stat 0 + txs + php + lda $1ff + cmp_flag 0 + + ldx #1 + txs ;sp=01 + set_stat $ff + tsx ;clears Z, N + php ;sp=00 + cpx #1 + trap_ne + lda $101 + cmp_flag $ff-minus-zero + trap_ne + set_stat $ff + tsx ;clears N, sets Z + php ;sp=ff + cpx #0 + trap_ne + lda $100 + cmp_flag $ff-minus + trap_ne + set_stat $ff + tsx ;clears N, sets Z + php ;sp=fe + cpx #$ff + trap_ne + lda $1ff + cmp_flag $ff-zero + trap_ne + + ldx #1 + txs ;sp=01 + set_stat 0 + tsx ;clears Z, N + php ;sp=00 + cpx #1 + trap_ne + lda $101 + cmp_flag 0 + trap_ne + set_stat 0 + tsx ;clears N, sets Z + php ;sp=ff + cpx #0 + trap_ne + lda $100 + cmp_flag zero + trap_ne + set_stat 0 + tsx ;clears N, sets Z + php ;sp=fe + cpx #$ff + trap_ne + lda $1ff + cmp_flag minus + trap_ne + pla ;sp=ff + next_test + +; testing index register load & store LDY LDX STY STX all addressing modes +; LDX / STX - zp,y / abs,y + ldy #3 +tldx + set_stat 0 + ldx zp1,y + php ;test stores do not alter flags + txa + eor #$c3 + plp + sta abst,y + php ;flags after load/store sequence + eor #$c3 + cmp abs1,y ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,y ;test flags + trap_ne + dey + bpl tldx + + ldy #3 +tldx1 + set_stat $ff + ldx zp1,y + php ;test stores do not alter flags + txa + eor #$c3 + plp + sta abst,y + php ;flags after load/store sequence + eor #$c3 + cmp abs1,y ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,y ;test flags + trap_ne + dey + bpl tldx1 + + ldy #3 +tldx2 + set_stat 0 + ldx abs1,y + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt,y + php ;flags after load/store sequence + eor #$c3 + cmp zp1,y ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,y ;test flags + trap_ne + dey + bpl tldx2 + + ldy #3 +tldx3 + set_stat $ff + ldx abs1,y + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt,y + php ;flags after load/store sequence + eor #$c3 + cmp zp1,y ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,y ;test flags + trap_ne + dey + bpl tldx3 + + ldy #3 ;testing store result + ldx #0 +tstx lda zpt,y + eor #$c3 + cmp zp1,y + trap_ne ;store to zp data + stx zpt,y ;clear + lda abst,y + eor #$c3 + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstx + next_test + +; indexed wraparound test (only zp should wrap) + ldy #3+$fa +tldx4 ldx zp1-$fa&$ff,y ;wrap on indexed zp + txa + sta abst-$fa,y ;no STX abs,y! + dey + cpy #$fa + bcs tldx4 + ldy #3+$fa +tldx5 ldx abs1-$fa,y ;no wrap on indexed abs + stx zpt-$fa&$ff,y + dey + cpy #$fa + bcs tldx5 + ldy #3 ;testing wraparound result + ldx #0 +tstx1 lda zpt,y + cmp zp1,y + trap_ne ;store to zp data + stx zpt,y ;clear + lda abst,y + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstx1 + next_test + +; LDY / STY - zp,x / abs,x + ldx #3 +tldy + set_stat 0 + ldy zp1,x + php ;test stores do not alter flags + tya + eor #$c3 + plp + sta abst,x + php ;flags after load/store sequence + eor #$c3 + cmp abs1,x ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldy + + ldx #3 +tldy1 + set_stat $ff + ldy zp1,x + php ;test stores do not alter flags + tya + eor #$c3 + plp + sta abst,x + php ;flags after load/store sequence + eor #$c3 + cmp abs1,x ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldy1 + + ldx #3 +tldy2 + set_stat 0 + ldy abs1,x + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt,x + php ;flags after load/store sequence + eor #$c3 + cmp zp1,x ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldy2 + + ldx #3 +tldy3 + set_stat $ff + ldy abs1,x + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt,x + php ;flags after load/store sequence + eor #$c3 + cmp zp1,x ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldy3 + + ldx #3 ;testing store result + ldy #0 +tsty lda zpt,x + eor #$c3 + cmp zp1,x + trap_ne ;store to zp,x data + sty zpt,x ;clear + lda abst,x + eor #$c3 + cmp abs1,x + trap_ne ;store to abs,x data + txa + sta abst,x ;clear + dex + bpl tsty + next_test + +; indexed wraparound test (only zp should wrap) + ldx #3+$fa +tldy4 ldy zp1-$fa&$ff,x ;wrap on indexed zp + tya + sta abst-$fa,x ;no STX abs,x! + dex + cpx #$fa + bcs tldy4 + ldx #3+$fa +tldy5 ldy abs1-$fa,x ;no wrap on indexed abs + sty zpt-$fa&$ff,x + dex + cpx #$fa + bcs tldy5 + ldx #3 ;testing wraparound result + ldy #0 +tsty1 lda zpt,x + cmp zp1,x + trap_ne ;store to zp,x data + sty zpt,x ;clear + lda abst,x + cmp abs1,x + trap_ne ;store to abs,x data + txa + sta abst,x ;clear + dex + bpl tsty1 + next_test + +; LDX / STX - zp / abs / # + set_stat 0 + ldx zp1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst + php ;flags after load/store sequence + eor #$c3 + tax + cpx #$c3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + ldx zp1+1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst+1 + php ;flags after load/store sequence + eor #$c3 + tax + cpx #$82 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + ldx zp1+2 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst+2 + php ;flags after load/store sequence + eor #$c3 + tax + cpx #$41 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + ldx zp1+3 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst+3 + php ;flags after load/store sequence + eor #$c3 + tax + cpx #0 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + + set_stat $ff + ldx zp1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst + php ;flags after load/store sequence + eor #$c3 + tax + cpx #$c3 ;test result + trap_ne ; + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + ldx zp1+1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst+1 + php ;flags after load/store sequence + eor #$c3 + tax + cpx #$82 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + ldx zp1+2 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst+2 + php ;flags after load/store sequence + eor #$c3 + tax + cpx #$41 ;test result + trap_ne ; + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + ldx zp1+3 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst+3 + php ;flags after load/store sequence + eor #$c3 + tax + cpx #0 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + + set_stat 0 + ldx abs1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt + php ;flags after load/store sequence + eor #$c3 + cmp zp1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + ldx abs1+1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt+1 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + ldx abs1+2 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt+2 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+2 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + ldx abs1+3 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt+3 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + + set_stat $ff + ldx abs1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt + php ;flags after load/store sequence + eor #$c3 + tax + cpx zp1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + ldx abs1+1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt+1 + php ;flags after load/store sequence + eor #$c3 + tax + cpx zp1+1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + ldx abs1+2 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt+2 + php ;flags after load/store sequence + eor #$c3 + tax + cpx zp1+2 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + ldx abs1+3 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt+3 + php ;flags after load/store sequence + eor #$c3 + tax + cpx zp1+3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + + set_stat 0 + ldx #$c3 + php + cpx abs1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + ldx #$82 + php + cpx abs1+1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + ldx #$41 + php + cpx abs1+2 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + ldx #0 + php + cpx abs1+3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + + set_stat $ff + ldx #$c3 + php + cpx abs1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + ldx #$82 + php + cpx abs1+1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + ldx #$41 + php + cpx abs1+2 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + ldx #0 + php + cpx abs1+3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + + ldx #0 + lda zpt + eor #$c3 + cmp zp1 + trap_ne ;store to zp data + stx zpt ;clear + lda abst + eor #$c3 + cmp abs1 + trap_ne ;store to abs data + stx abst ;clear + lda zpt+1 + eor #$c3 + cmp zp1+1 + trap_ne ;store to zp data + stx zpt+1 ;clear + lda abst+1 + eor #$c3 + cmp abs1+1 + trap_ne ;store to abs data + stx abst+1 ;clear + lda zpt+2 + eor #$c3 + cmp zp1+2 + trap_ne ;store to zp data + stx zpt+2 ;clear + lda abst+2 + eor #$c3 + cmp abs1+2 + trap_ne ;store to abs data + stx abst+2 ;clear + lda zpt+3 + eor #$c3 + cmp zp1+3 + trap_ne ;store to zp data + stx zpt+3 ;clear + lda abst+3 + eor #$c3 + cmp abs1+3 + trap_ne ;store to abs data + stx abst+3 ;clear + next_test + +; LDY / STY - zp / abs / # + set_stat 0 + ldy zp1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst + php ;flags after load/store sequence + eor #$c3 + tay + cpy #$c3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + ldy zp1+1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst+1 + php ;flags after load/store sequence + eor #$c3 + tay + cpy #$82 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + ldy zp1+2 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst+2 + php ;flags after load/store sequence + eor #$c3 + tay + cpy #$41 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + ldy zp1+3 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst+3 + php ;flags after load/store sequence + eor #$c3 + tay + cpy #0 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + + set_stat $ff + ldy zp1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst + php ;flags after load/store sequence + eor #$c3 + tay + cpy #$c3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + ldy zp1+1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst+1 + php ;flags after load/store sequence + eor #$c3 + tay + cpy #$82 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + ldy zp1+2 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst+2 + php ;flags after load/store sequence + eor #$c3 + tay + cpy #$41 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + ldy zp1+3 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst+3 + php ;flags after load/store sequence + eor #$c3 + tay + cpy #0 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + + set_stat 0 + ldy abs1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt + php ;flags after load/store sequence + eor #$c3 + tay + cpy zp1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + ldy abs1+1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt+1 + php ;flags after load/store sequence + eor #$c3 + tay + cpy zp1+1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + ldy abs1+2 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt+2 + php ;flags after load/store sequence + eor #$c3 + tay + cpy zp1+2 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + ldy abs1+3 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt+3 + php ;flags after load/store sequence + eor #$c3 + tay + cpy zp1+3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + + set_stat $ff + ldy abs1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt + php ;flags after load/store sequence + eor #$c3 + tay + cmp zp1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + ldy abs1+1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt+1 + php ;flags after load/store sequence + eor #$c3 + tay + cmp zp1+1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + ldy abs1+2 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt+2 + php ;flags after load/store sequence + eor #$c3 + tay + cmp zp1+2 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + ldy abs1+3 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt+3 + php ;flags after load/store sequence + eor #$c3 + tay + cmp zp1+3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + + + set_stat 0 + ldy #$c3 + php + cpy abs1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + ldy #$82 + php + cpy abs1+1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + ldy #$41 + php + cpy abs1+2 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + ldy #0 + php + cpy abs1+3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + + set_stat $ff + ldy #$c3 + php + cpy abs1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + ldy #$82 + php + cpy abs1+1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + ldy #$41 + php + cpy abs1+2 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + ldy #0 + php + cpy abs1+3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + + ldy #0 + lda zpt + eor #$c3 + cmp zp1 + trap_ne ;store to zp data + sty zpt ;clear + lda abst + eor #$c3 + cmp abs1 + trap_ne ;store to abs data + sty abst ;clear + lda zpt+1 + eor #$c3 + cmp zp1+1 + trap_ne ;store to zp+1 data + sty zpt+1 ;clear + lda abst+1 + eor #$c3 + cmp abs1+1 + trap_ne ;store to abs+1 data + sty abst+1 ;clear + lda zpt+2 + eor #$c3 + cmp zp1+2 + trap_ne ;store to zp+2 data + sty zpt+2 ;clear + lda abst+2 + eor #$c3 + cmp abs1+2 + trap_ne ;store to abs+2 data + sty abst+2 ;clear + lda zpt+3 + eor #$c3 + cmp zp1+3 + trap_ne ;store to zp+3 data + sty zpt+3 ;clear + lda abst+3 + eor #$c3 + cmp abs1+3 + trap_ne ;store to abs+3 data + sty abst+3 ;clear + next_test + +; testing load / store accumulator LDA / STA all addressing modes +; LDA / STA - zp,x / abs,x + ldx #3 +tldax + set_stat 0 + lda zp1,x + php ;test stores do not alter flags + eor #$c3 + plp + sta abst,x + php ;flags after load/store sequence + eor #$c3 + cmp abs1,x ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldax + + ldx #3 +tldax1 + set_stat $ff + lda zp1,x + php ;test stores do not alter flags + eor #$c3 + plp + sta abst,x + php ;flags after load/store sequence + eor #$c3 + cmp abs1,x ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldax1 + + ldx #3 +tldax2 + set_stat 0 + lda abs1,x + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt,x + php ;flags after load/store sequence + eor #$c3 + cmp zp1,x ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldax2 + + ldx #3 +tldax3 + set_stat $ff + lda abs1,x + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt,x + php ;flags after load/store sequence + eor #$c3 + cmp zp1,x ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldax3 + + ldx #3 ;testing store result + ldy #0 +tstax lda zpt,x + eor #$c3 + cmp zp1,x + trap_ne ;store to zp,x data + sty zpt,x ;clear + lda abst,x + eor #$c3 + cmp abs1,x + trap_ne ;store to abs,x data + txa + sta abst,x ;clear + dex + bpl tstax + next_test + +; LDA / STA - (zp),y / abs,y / (zp,x) + ldy #3 +tlday + set_stat 0 + lda (ind1),y + php ;test stores do not alter flags + eor #$c3 + plp + sta abst,y + php ;flags after load/store sequence + eor #$c3 + cmp abs1,y ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,y ;test flags + trap_ne + dey + bpl tlday + + ldy #3 +tlday1 + set_stat $ff + lda (ind1),y + php ;test stores do not alter flags + eor #$c3 + plp + sta abst,y + php ;flags after load/store sequence + eor #$c3 + cmp abs1,y ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,y ;test flags + trap_ne + dey + bpl tlday1 + + ldy #3 ;testing store result + ldx #0 +tstay lda abst,y + eor #$c3 + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstay + + ldy #3 +tlday2 + set_stat 0 + lda abs1,y + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt),y + php ;flags after load/store sequence + eor #$c3 + cmp (ind1),y ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,y ;test flags + trap_ne + dey + bpl tlday2 + + ldy #3 +tlday3 + set_stat $ff + lda abs1,y + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt),y + php ;flags after load/store sequence + eor #$c3 + cmp (ind1),y ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,y ;test flags + trap_ne + dey + bpl tlday3 + + ldy #3 ;testing store result + ldx #0 +tstay1 lda abst,y + eor #$c3 + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstay1 + + ldx #6 + ldy #3 +tldax4 + set_stat 0 + lda (ind1,x) + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt,x) + php ;flags after load/store sequence + eor #$c3 + cmp abs1,y ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,y ;test flags + trap_ne + dex + dex + dey + bpl tldax4 + + ldx #6 + ldy #3 +tldax5 + set_stat $ff + lda (ind1,x) + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt,x) + php ;flags after load/store sequence + eor #$c3 + cmp abs1,y ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,y ;test flags + trap_ne + dex + dex + dey + bpl tldax5 + + ldy #3 ;testing store result + ldx #0 +tstay2 lda abst,y + eor #$c3 + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstay2 + next_test + +; indexed wraparound test (only zp should wrap) + ldx #3+$fa +tldax6 lda zp1-$fa&$ff,x ;wrap on indexed zp + sta abst-$fa,x ;no STX abs,x! + dex + cpx #$fa + bcs tldax6 + ldx #3+$fa +tldax7 lda abs1-$fa,x ;no wrap on indexed abs + sta zpt-$fa&$ff,x + dex + cpx #$fa + bcs tldax7 + + ldx #3 ;testing wraparound result + ldy #0 +tstax1 lda zpt,x + cmp zp1,x + trap_ne ;store to zp,x data + sty zpt,x ;clear + lda abst,x + cmp abs1,x + trap_ne ;store to abs,x data + txa + sta abst,x ;clear + dex + bpl tstax1 + + ldy #3+$f8 + ldx #6+$f8 +tlday4 lda (ind1-$f8&$ff,x) ;wrap on indexed zp indirect + sta abst-$f8,y + dex + dex + dey + cpy #$f8 + bcs tlday4 + ldy #3 ;testing wraparound result + ldx #0 +tstay4 lda abst,y + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstay4 + + ldy #3+$f8 +tlday5 lda abs1-$f8,y ;no wrap on indexed abs + sta (inwt),y + dey + cpy #$f8 + bcs tlday5 + ldy #3 ;testing wraparound result + ldx #0 +tstay5 lda abst,y + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstay5 + + ldy #3+$f8 + ldx #6+$f8 +tlday6 lda (inw1),y ;no wrap on zp indirect indexed + sta (indt-$f8&$ff,x) + dex + dex + dey + cpy #$f8 + bcs tlday6 + ldy #3 ;testing wraparound result + ldx #0 +tstay6 lda abst,y + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstay6 + next_test + +; LDA / STA - zp / abs / # + set_stat 0 + lda zp1 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst + php ;flags after load/store sequence + eor #$c3 + cmp #$c3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + lda zp1+1 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst+1 + php ;flags after load/store sequence + eor #$c3 + cmp #$82 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + lda zp1+2 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst+2 + php ;flags after load/store sequence + eor #$c3 + cmp #$41 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + lda zp1+3 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst+3 + php ;flags after load/store sequence + eor #$c3 + cmp #0 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + set_stat $ff + lda zp1 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst + php ;flags after load/store sequence + eor #$c3 + cmp #$c3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + lda zp1+1 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst+1 + php ;flags after load/store sequence + eor #$c3 + cmp #$82 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + lda zp1+2 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst+2 + php ;flags after load/store sequence + eor #$c3 + cmp #$41 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + lda zp1+3 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst+3 + php ;flags after load/store sequence + eor #$c3 + cmp #0 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + set_stat 0 + lda abs1 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt + php ;flags after load/store sequence + eor #$c3 + cmp zp1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + lda abs1+1 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt+1 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + lda abs1+2 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt+2 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+2 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + lda abs1+3 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt+3 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + set_stat $ff + lda abs1 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt + php ;flags after load/store sequence + eor #$c3 + cmp zp1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + lda abs1+1 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt+1 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + lda abs1+2 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt+2 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+2 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + lda abs1+3 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt+3 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + set_stat 0 + lda #$c3 + php + cmp abs1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + lda #$82 + php + cmp abs1+1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + lda #$41 + php + cmp abs1+2 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + lda #0 + php + cmp abs1+3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + + set_stat $ff + lda #$c3 + php + cmp abs1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + lda #$82 + php + cmp abs1+1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + lda #$41 + php + cmp abs1+2 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + lda #0 + php + cmp abs1+3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + + ldx #0 + lda zpt + eor #$c3 + cmp zp1 + trap_ne ;store to zp data + stx zpt ;clear + lda abst + eor #$c3 + cmp abs1 + trap_ne ;store to abs data + stx abst ;clear + lda zpt+1 + eor #$c3 + cmp zp1+1 + trap_ne ;store to zp data + stx zpt+1 ;clear + lda abst+1 + eor #$c3 + cmp abs1+1 + trap_ne ;store to abs data + stx abst+1 ;clear + lda zpt+2 + eor #$c3 + cmp zp1+2 + trap_ne ;store to zp data + stx zpt+2 ;clear + lda abst+2 + eor #$c3 + cmp abs1+2 + trap_ne ;store to abs data + stx abst+2 ;clear + lda zpt+3 + eor #$c3 + cmp zp1+3 + trap_ne ;store to zp data + stx zpt+3 ;clear + lda abst+3 + eor #$c3 + cmp abs1+3 + trap_ne ;store to abs data + stx abst+3 ;clear + next_test + +; testing bit test & compares BIT CPX CPY CMP all addressing modes +; BIT - zp / abs + set_a $ff,0 + bit zp1+3 ;00 - should set Z / clear NV + tst_a $ff,fz + set_a 1,0 + bit zp1+2 ;41 - should set V (M6) / clear NZ + tst_a 1,fv + set_a 1,0 + bit zp1+1 ;82 - should set N (M7) & Z / clear V + tst_a 1,fnz + set_a 1,0 + bit zp1 ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,fnv + + set_a $ff,$ff + bit zp1+3 ;00 - should set Z / clear NV + tst_a $ff,~fnv + set_a 1,$ff + bit zp1+2 ;41 - should set V (M6) / clear NZ + tst_a 1,~fnz + set_a 1,$ff + bit zp1+1 ;82 - should set N (M7) & Z / clear V + tst_a 1,~fv + set_a 1,$ff + bit zp1 ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,~fz + + set_a $ff,0 + bit abs1+3 ;00 - should set Z / clear NV + tst_a $ff,fz + set_a 1,0 + bit abs1+2 ;41 - should set V (M6) / clear NZ + tst_a 1,fv + set_a 1,0 + bit abs1+1 ;82 - should set N (M7) & Z / clear V + tst_a 1,fnz + set_a 1,0 + bit abs1 ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,fnv + + set_a $ff,$ff + bit abs1+3 ;00 - should set Z / clear NV + tst_a $ff,~fnv + set_a 1,$ff + bit abs1+2 ;41 - should set V (M6) / clear NZ + tst_a 1,~fnz + set_a 1,$ff + bit abs1+1 ;82 - should set N (M7) & Z / clear V + tst_a 1,~fv + set_a 1,$ff + bit abs1 ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,~fz + next_test + +; CPX - zp / abs / # + set_x $80,0 + cpx zp7f + tst_stat fc + dex + cpx zp7f + tst_stat fzc + dex + cpx zp7f + tst_x $7e,fn + set_x $80,$ff + cpx zp7f + tst_stat ~fnz + dex + cpx zp7f + tst_stat ~fn + dex + cpx zp7f + tst_x $7e,~fzc + + set_x $80,0 + cpx abs7f + tst_stat fc + dex + cpx abs7f + tst_stat fzc + dex + cpx abs7f + tst_x $7e,fn + set_x $80,$ff + cpx abs7f + tst_stat ~fnz + dex + cpx abs7f + tst_stat ~fn + dex + cpx abs7f + tst_x $7e,~fzc + + set_x $80,0 + cpx #$7f + tst_stat fc + dex + cpx #$7f + tst_stat fzc + dex + cpx #$7f + tst_x $7e,fn + set_x $80,$ff + cpx #$7f + tst_stat ~fnz + dex + cpx #$7f + tst_stat ~fn + dex + cpx #$7f + tst_x $7e,~fzc + next_test + +; CPY - zp / abs / # + set_y $80,0 + cpy zp7f + tst_stat fc + dey + cpy zp7f + tst_stat fzc + dey + cpy zp7f + tst_y $7e,fn + set_y $80,$ff + cpy zp7f + tst_stat ~fnz + dey + cpy zp7f + tst_stat ~fn + dey + cpy zp7f + tst_y $7e,~fzc + + set_y $80,0 + cpy abs7f + tst_stat fc + dey + cpy abs7f + tst_stat fzc + dey + cpy abs7f + tst_y $7e,fn + set_y $80,$ff + cpy abs7f + tst_stat ~fnz + dey + cpy abs7f + tst_stat ~fn + dey + cpy abs7f + tst_y $7e,~fzc + + set_y $80,0 + cpy #$7f + tst_stat fc + dey + cpy #$7f + tst_stat fzc + dey + cpy #$7f + tst_y $7e,fn + set_y $80,$ff + cpy #$7f + tst_stat ~fnz + dey + cpy #$7f + tst_stat ~fn + dey + cpy #$7f + tst_y $7e,~fzc + next_test + +; CMP - zp / abs / # + set_a $80,0 + cmp zp7f + tst_a $80,fc + set_a $7f,0 + cmp zp7f + tst_a $7f,fzc + set_a $7e,0 + cmp zp7f + tst_a $7e,fn + set_a $80,$ff + cmp zp7f + tst_a $80,~fnz + set_a $7f,$ff + cmp zp7f + tst_a $7f,~fn + set_a $7e,$ff + cmp zp7f + tst_a $7e,~fzc + + set_a $80,0 + cmp abs7f + tst_a $80,fc + set_a $7f,0 + cmp abs7f + tst_a $7f,fzc + set_a $7e,0 + cmp abs7f + tst_a $7e,fn + set_a $80,$ff + cmp abs7f + tst_a $80,~fnz + set_a $7f,$ff + cmp abs7f + tst_a $7f,~fn + set_a $7e,$ff + cmp abs7f + tst_a $7e,~fzc + + set_a $80,0 + cmp #$7f + tst_a $80,fc + set_a $7f,0 + cmp #$7f + tst_a $7f,fzc + set_a $7e,0 + cmp #$7f + tst_a $7e,fn + set_a $80,$ff + cmp #$7f + tst_a $80,~fnz + set_a $7f,$ff + cmp #$7f + tst_a $7f,~fn + set_a $7e,$ff + cmp #$7f + tst_a $7e,~fzc + + ldx #4 ;with indexing by X + set_a $80,0 + cmp zp1,x + tst_a $80,fc + set_a $7f,0 + cmp zp1,x + tst_a $7f,fzc + set_a $7e,0 + cmp zp1,x + tst_a $7e,fn + set_a $80,$ff + cmp zp1,x + tst_a $80,~fnz + set_a $7f,$ff + cmp zp1,x + tst_a $7f,~fn + set_a $7e,$ff + cmp zp1,x + tst_a $7e,~fzc + + set_a $80,0 + cmp abs1,x + tst_a $80,fc + set_a $7f,0 + cmp abs1,x + tst_a $7f,fzc + set_a $7e,0 + cmp abs1,x + tst_a $7e,fn + set_a $80,$ff + cmp abs1,x + tst_a $80,~fnz + set_a $7f,$ff + cmp abs1,x + tst_a $7f,~fn + set_a $7e,$ff + cmp abs1,x + tst_a $7e,~fzc + + ldy #4 ;with indexing by Y + ldx #8 ;with indexed indirect + set_a $80,0 + cmp abs1,y + tst_a $80,fc + set_a $7f,0 + cmp abs1,y + tst_a $7f,fzc + set_a $7e,0 + cmp abs1,y + tst_a $7e,fn + set_a $80,$ff + cmp abs1,y + tst_a $80,~fnz + set_a $7f,$ff + cmp abs1,y + tst_a $7f,~fn + set_a $7e,$ff + cmp abs1,y + tst_a $7e,~fzc + + set_a $80,0 + cmp (ind1,x) + tst_a $80,fc + set_a $7f,0 + cmp (ind1,x) + tst_a $7f,fzc + set_a $7e,0 + cmp (ind1,x) + tst_a $7e,fn + set_a $80,$ff + cmp (ind1,x) + tst_a $80,~fnz + set_a $7f,$ff + cmp (ind1,x) + tst_a $7f,~fn + set_a $7e,$ff + cmp (ind1,x) + tst_a $7e,~fzc + + set_a $80,0 + cmp (ind1),y + tst_a $80,fc + set_a $7f,0 + cmp (ind1),y + tst_a $7f,fzc + set_a $7e,0 + cmp (ind1),y + tst_a $7e,fn + set_a $80,$ff + cmp (ind1),y + tst_a $80,~fnz + set_a $7f,$ff + cmp (ind1),y + tst_a $7f,~fn + set_a $7e,$ff + cmp (ind1),y + tst_a $7e,~fzc + next_test + +; testing shifts - ASL LSR ROL ROR all addressing modes +; shifts - accumulator + ldx #5 +tasl + set_ax zps,0 + asl a + tst_ax rASL,fASL,0 + dex + bpl tasl + ldx #5 +tasl1 + set_ax zps,$ff + asl a + tst_ax rASL,fASL,$ff-fnzc + dex + bpl tasl1 + + ldx #5 +tlsr + set_ax zps,0 + lsr a + tst_ax rLSR,fLSR,0 + dex + bpl tlsr + ldx #5 +tlsr1 + set_ax zps,$ff + lsr a + tst_ax rLSR,fLSR,$ff-fnzc + dex + bpl tlsr1 + + ldx #5 +trol + set_ax zps,0 + rol a + tst_ax rROL,fROL,0 + dex + bpl trol + ldx #5 +trol1 + set_ax zps,$ff-fc + rol a + tst_ax rROL,fROL,$ff-fnzc + dex + bpl trol1 + + ldx #5 +trolc + set_ax zps,fc + rol a + tst_ax rROLc,fROLc,0 + dex + bpl trolc + ldx #5 +trolc1 + set_ax zps,$ff + rol a + tst_ax rROLc,fROLc,$ff-fnzc + dex + bpl trolc1 + + ldx #5 +tror + set_ax zps,0 + ror a + tst_ax rROR,fROR,0 + dex + bpl tror + ldx #5 +tror1 + set_ax zps,$ff-fc + ror a + tst_ax rROR,fROR,$ff-fnzc + dex + bpl tror1 + + ldx #5 +trorc + set_ax zps,fc + ror a + tst_ax rRORc,fRORc,0 + dex + bpl trorc + ldx #5 +trorc1 + set_ax zps,$ff + ror a + tst_ax rRORc,fRORc,$ff-fnzc + dex + bpl trorc1 + next_test + +; shifts - zeropage + ldx #5 +tasl2 + set_z zps,0 + asl zpt + tst_z rASL,fASL,0 + dex + bpl tasl2 + ldx #5 +tasl3 + set_z zps,$ff + asl zpt + tst_z rASL,fASL,$ff-fnzc + dex + bpl tasl3 + + ldx #5 +tlsr2 + set_z zps,0 + lsr zpt + tst_z rLSR,fLSR,0 + dex + bpl tlsr2 + ldx #5 +tlsr3 + set_z zps,$ff + lsr zpt + tst_z rLSR,fLSR,$ff-fnzc + dex + bpl tlsr3 + + ldx #5 +trol2 + set_z zps,0 + rol zpt + tst_z rROL,fROL,0 + dex + bpl trol2 + ldx #5 +trol3 + set_z zps,$ff-fc + rol zpt + tst_z rROL,fROL,$ff-fnzc + dex + bpl trol3 + + ldx #5 +trolc2 + set_z zps,fc + rol zpt + tst_z rROLc,fROLc,0 + dex + bpl trolc2 + ldx #5 +trolc3 + set_z zps,$ff + rol zpt + tst_z rROLc,fROLc,$ff-fnzc + dex + bpl trolc3 + + ldx #5 +tror2 + set_z zps,0 + ror zpt + tst_z rROR,fROR,0 + dex + bpl tror2 + ldx #5 +tror3 + set_z zps,$ff-fc + ror zpt + tst_z rROR,fROR,$ff-fnzc + dex + bpl tror3 + + ldx #5 +trorc2 + set_z zps,fc + ror zpt + tst_z rRORc,fRORc,0 + dex + bpl trorc2 + ldx #5 +trorc3 + set_z zps,$ff + ror zpt + tst_z rRORc,fRORc,$ff-fnzc + dex + bpl trorc3 + next_test + +; shifts - absolute + ldx #5 +tasl4 + set_abs zps,0 + asl abst + tst_abs rASL,fASL,0 + dex + bpl tasl4 + ldx #5 +tasl5 + set_abs zps,$ff + asl abst + tst_abs rASL,fASL,$ff-fnzc + dex + bpl tasl5 + + ldx #5 +tlsr4 + set_abs zps,0 + lsr abst + tst_abs rLSR,fLSR,0 + dex + bpl tlsr4 + ldx #5 +tlsr5 + set_abs zps,$ff + lsr abst + tst_abs rLSR,fLSR,$ff-fnzc + dex + bpl tlsr5 + + ldx #5 +trol4 + set_abs zps,0 + rol abst + tst_abs rROL,fROL,0 + dex + bpl trol4 + ldx #5 +trol5 + set_abs zps,$ff-fc + rol abst + tst_abs rROL,fROL,$ff-fnzc + dex + bpl trol5 + + ldx #5 +trolc4 + set_abs zps,fc + rol abst + tst_abs rROLc,fROLc,0 + dex + bpl trolc4 + ldx #5 +trolc5 + set_abs zps,$ff + rol abst + tst_abs rROLc,fROLc,$ff-fnzc + dex + bpl trolc5 + + ldx #5 +tror4 + set_abs zps,0 + ror abst + tst_abs rROR,fROR,0 + dex + bpl tror4 + ldx #5 +tror5 + set_abs zps,$ff-fc + ror abst + tst_abs rROR,fROR,$ff-fnzc + dex + bpl tror5 + + ldx #5 +trorc4 + set_abs zps,fc + ror abst + tst_abs rRORc,fRORc,0 + dex + bpl trorc4 + ldx #5 +trorc5 + set_abs zps,$ff + ror abst + tst_abs rRORc,fRORc,$ff-fnzc + dex + bpl trorc5 + next_test + +; shifts - zp indexed + ldx #5 +tasl6 + set_zx zps,0 + asl zpt,x + tst_zx rASL,fASL,0 + dex + bpl tasl6 + ldx #5 +tasl7 + set_zx zps,$ff + asl zpt,x + tst_zx rASL,fASL,$ff-fnzc + dex + bpl tasl7 + + ldx #5 +tlsr6 + set_zx zps,0 + lsr zpt,x + tst_zx rLSR,fLSR,0 + dex + bpl tlsr6 + ldx #5 +tlsr7 + set_zx zps,$ff + lsr zpt,x + tst_zx rLSR,fLSR,$ff-fnzc + dex + bpl tlsr7 + + ldx #5 +trol6 + set_zx zps,0 + rol zpt,x + tst_zx rROL,fROL,0 + dex + bpl trol6 + ldx #5 +trol7 + set_zx zps,$ff-fc + rol zpt,x + tst_zx rROL,fROL,$ff-fnzc + dex + bpl trol7 + + ldx #5 +trolc6 + set_zx zps,fc + rol zpt,x + tst_zx rROLc,fROLc,0 + dex + bpl trolc6 + ldx #5 +trolc7 + set_zx zps,$ff + rol zpt,x + tst_zx rROLc,fROLc,$ff-fnzc + dex + bpl trolc7 + + ldx #5 +tror6 + set_zx zps,0 + ror zpt,x + tst_zx rROR,fROR,0 + dex + bpl tror6 + ldx #5 +tror7 + set_zx zps,$ff-fc + ror zpt,x + tst_zx rROR,fROR,$ff-fnzc + dex + bpl tror7 + + ldx #5 +trorc6 + set_zx zps,fc + ror zpt,x + tst_zx rRORc,fRORc,0 + dex + bpl trorc6 + ldx #5 +trorc7 + set_zx zps,$ff + ror zpt,x + tst_zx rRORc,fRORc,$ff-fnzc + dex + bpl trorc7 + next_test + +; shifts - abs indexed + ldx #5 +tasl8 + set_absx zps,0 + asl abst,x + tst_absx rASL,fASL,0 + dex + bpl tasl8 + ldx #5 +tasl9 + set_absx zps,$ff + asl abst,x + tst_absx rASL,fASL,$ff-fnzc + dex + bpl tasl9 + + ldx #5 +tlsr8 + set_absx zps,0 + lsr abst,x + tst_absx rLSR,fLSR,0 + dex + bpl tlsr8 + ldx #5 +tlsr9 + set_absx zps,$ff + lsr abst,x + tst_absx rLSR,fLSR,$ff-fnzc + dex + bpl tlsr9 + + ldx #5 +trol8 + set_absx zps,0 + rol abst,x + tst_absx rROL,fROL,0 + dex + bpl trol8 + ldx #5 +trol9 + set_absx zps,$ff-fc + rol abst,x + tst_absx rROL,fROL,$ff-fnzc + dex + bpl trol9 + + ldx #5 +trolc8 + set_absx zps,fc + rol abst,x + tst_absx rROLc,fROLc,0 + dex + bpl trolc8 + ldx #5 +trolc9 + set_absx zps,$ff + rol abst,x + tst_absx rROLc,fROLc,$ff-fnzc + dex + bpl trolc9 + + ldx #5 +tror8 + set_absx zps,0 + ror abst,x + tst_absx rROR,fROR,0 + dex + bpl tror8 + ldx #5 +tror9 + set_absx zps,$ff-fc + ror abst,x + tst_absx rROR,fROR,$ff-fnzc + dex + bpl tror9 + + ldx #5 +trorc8 + set_absx zps,fc + ror abst,x + tst_absx rRORc,fRORc,0 + dex + bpl trorc8 + ldx #5 +trorc9 + set_absx zps,$ff + ror abst,x + tst_absx rRORc,fRORc,$ff-fnzc + dex + bpl trorc9 + next_test + +; testing memory increment/decrement - INC DEC all addressing modes +; zeropage + ldx #0 + lda #$7e + sta zpt +tinc + set_stat 0 + inc zpt + tst_z rINC,fINC,0 + inx + cpx #2 + bne tinc1 + lda #$fe + sta zpt +tinc1 cpx #5 + bne tinc + dex + inc zpt +tdec + set_stat 0 + dec zpt + tst_z rINC,fINC,0 + dex + bmi tdec1 + cpx #1 + bne tdec + lda #$81 + sta zpt + bne tdec +tdec1 + ldx #0 + lda #$7e + sta zpt +tinc10 + set_stat $ff + inc zpt + tst_z rINC,fINC,$ff-fnz + inx + cpx #2 + bne tinc11 + lda #$fe + sta zpt +tinc11 cpx #5 + bne tinc10 + dex + inc zpt +tdec10 + set_stat $ff + dec zpt + tst_z rINC,fINC,$ff-fnz + dex + bmi tdec11 + cpx #1 + bne tdec10 + lda #$81 + sta zpt + bne tdec10 +tdec11 + next_test + +; absolute memory + ldx #0 + lda #$7e + sta abst +tinc2 + set_stat 0 + inc abst + tst_abs rINC,fINC,0 + inx + cpx #2 + bne tinc3 + lda #$fe + sta abst +tinc3 cpx #5 + bne tinc2 + dex + inc abst +tdec2 + set_stat 0 + dec abst + tst_abs rINC,fINC,0 + dex + bmi tdec3 + cpx #1 + bne tdec2 + lda #$81 + sta abst + bne tdec2 +tdec3 + ldx #0 + lda #$7e + sta abst +tinc12 + set_stat $ff + inc abst + tst_abs rINC,fINC,$ff-fnz + inx + cpx #2 + bne tinc13 + lda #$fe + sta abst +tinc13 cpx #5 + bne tinc12 + dex + inc abst +tdec12 + set_stat $ff + dec abst + tst_abs rINC,fINC,$ff-fnz + dex + bmi tdec13 + cpx #1 + bne tdec12 + lda #$81 + sta abst + bne tdec12 +tdec13 + next_test + +; zeropage indexed + ldx #0 + lda #$7e +tinc4 sta zpt,x + set_stat 0 + inc zpt,x + tst_zx rINC,fINC,0 + lda zpt,x + inx + cpx #2 + bne tinc5 + lda #$fe +tinc5 cpx #5 + bne tinc4 + dex + lda #2 +tdec4 sta zpt,x + set_stat 0 + dec zpt,x + tst_zx rINC,fINC,0 + lda zpt,x + dex + bmi tdec5 + cpx #1 + bne tdec4 + lda #$81 + bne tdec4 +tdec5 + ldx #0 + lda #$7e +tinc14 sta zpt,x + set_stat $ff + inc zpt,x + tst_zx rINC,fINC,$ff-fnz + lda zpt,x + inx + cpx #2 + bne tinc15 + lda #$fe +tinc15 cpx #5 + bne tinc14 + dex + lda #2 +tdec14 sta zpt,x + set_stat $ff + dec zpt,x + tst_zx rINC,fINC,$ff-fnz + lda zpt,x + dex + bmi tdec15 + cpx #1 + bne tdec14 + lda #$81 + bne tdec14 +tdec15 + next_test + +; memory indexed + ldx #0 + lda #$7e +tinc6 sta abst,x + set_stat 0 + inc abst,x + tst_absx rINC,fINC,0 + lda abst,x + inx + cpx #2 + bne tinc7 + lda #$fe +tinc7 cpx #5 + bne tinc6 + dex + lda #2 +tdec6 sta abst,x + set_stat 0 + dec abst,x + tst_absx rINC,fINC,0 + lda abst,x + dex + bmi tdec7 + cpx #1 + bne tdec6 + lda #$81 + bne tdec6 +tdec7 + ldx #0 + lda #$7e +tinc16 sta abst,x + set_stat $ff + inc abst,x + tst_absx rINC,fINC,$ff-fnz + lda abst,x + inx + cpx #2 + bne tinc17 + lda #$fe +tinc17 cpx #5 + bne tinc16 + dex + lda #2 +tdec16 sta abst,x + set_stat $ff + dec abst,x + tst_absx rINC,fINC,$ff-fnz + lda abst,x + dex + bmi tdec17 + cpx #1 + bne tdec16 + lda #$81 + bne tdec16 +tdec17 + next_test + +; testing logical instructions - AND EOR ORA all addressing modes +; AND + ldx #3 ;immediate +tand lda zpAN,x + sta ex_andi+1 ;set AND # operand + set_ax absANa,0 + jsr ex_andi ;execute AND # in RAM + tst_ax absrlo,absflo,0 + dex + bpl tand + ldx #3 +tand1 lda zpAN,x + sta ex_andi+1 ;set AND # operand + set_ax absANa,$ff + jsr ex_andi ;execute AND # in RAM + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tand1 + + ldx #3 ;zp +tand2 lda zpAN,x + sta zpt + set_ax absANa,0 + and zpt + tst_ax absrlo,absflo,0 + dex + bpl tand2 + ldx #3 +tand3 lda zpAN,x + sta zpt + set_ax absANa,$ff + and zpt + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tand3 + + ldx #3 ;abs +tand4 lda zpAN,x + sta abst + set_ax absANa,0 + and abst + tst_ax absrlo,absflo,0 + dex + bpl tand4 + ldx #3 +tand5 lda zpAN,x + sta abst + set_ax absANa,$ff + and abst + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tand6 + + ldx #3 ;zp,x +tand6 + set_ax absANa,0 + and zpAN,x + tst_ax absrlo,absflo,0 + dex + bpl tand6 + ldx #3 +tand7 + set_ax absANa,$ff + and zpAN,x + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tand7 + + ldx #3 ;abs,x +tand8 + set_ax absANa,0 + and absAN,x + tst_ax absrlo,absflo,0 + dex + bpl tand8 + ldx #3 +tand9 + set_ax absANa,$ff + and absAN,x + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tand9 + + ldy #3 ;abs,y +tand10 + set_ay absANa,0 + and absAN,y + tst_ay absrlo,absflo,0 + dey + bpl tand10 + ldy #3 +tand11 + set_ay absANa,$ff + and absAN,y + tst_ay absrlo,absflo,$ff-fnz + dey + bpl tand11 + + ldx #6 ;(zp,x) + ldy #3 +tand12 + set_ay absANa,0 + and (indAN,x) + tst_ay absrlo,absflo,0 + dex + dex + dey + bpl tand12 + ldx #6 + ldy #3 +tand13 + set_ay absANa,$ff + and (indAN,x) + tst_ay absrlo,absflo,$ff-fnz + dex + dex + dey + bpl tand13 + + ldy #3 ;(zp),y +tand14 + set_ay absANa,0 + and (indAN),y + tst_ay absrlo,absflo,0 + dey + bpl tand14 + ldy #3 +tand15 + set_ay absANa,$ff + and (indAN),y + tst_ay absrlo,absflo,$ff-fnz + dey + bpl tand15 + next_test + +; EOR + ldx #3 ;immediate - self modifying code +teor lda zpEO,x + sta ex_eori+1 ;set EOR # operand + set_ax absEOa,0 + jsr ex_eori ;execute EOR # in RAM + tst_ax absrlo,absflo,0 + dex + bpl teor + ldx #3 +teor1 lda zpEO,x + sta ex_eori+1 ;set EOR # operand + set_ax absEOa,$ff + jsr ex_eori ;execute EOR # in RAM + tst_ax absrlo,absflo,$ff-fnz + dex + bpl teor1 + + ldx #3 ;zp +teor2 lda zpEO,x + sta zpt + set_ax absEOa,0 + eor zpt + tst_ax absrlo,absflo,0 + dex + bpl teor2 + ldx #3 +teor3 lda zpEO,x + sta zpt + set_ax absEOa,$ff + eor zpt + tst_ax absrlo,absflo,$ff-fnz + dex + bpl teor3 + + ldx #3 ;abs +teor4 lda zpEO,x + sta abst + set_ax absEOa,0 + eor abst + tst_ax absrlo,absflo,0 + dex + bpl teor4 + ldx #3 +teor5 lda zpEO,x + sta abst + set_ax absEOa,$ff + eor abst + tst_ax absrlo,absflo,$ff-fnz + dex + bpl teor6 + + ldx #3 ;zp,x +teor6 + set_ax absEOa,0 + eor zpEO,x + tst_ax absrlo,absflo,0 + dex + bpl teor6 + ldx #3 +teor7 + set_ax absEOa,$ff + eor zpEO,x + tst_ax absrlo,absflo,$ff-fnz + dex + bpl teor7 + + ldx #3 ;abs,x +teor8 + set_ax absEOa,0 + eor absEO,x + tst_ax absrlo,absflo,0 + dex + bpl teor8 + ldx #3 +teor9 + set_ax absEOa,$ff + eor absEO,x + tst_ax absrlo,absflo,$ff-fnz + dex + bpl teor9 + + ldy #3 ;abs,y +teor10 + set_ay absEOa,0 + eor absEO,y + tst_ay absrlo,absflo,0 + dey + bpl teor10 + ldy #3 +teor11 + set_ay absEOa,$ff + eor absEO,y + tst_ay absrlo,absflo,$ff-fnz + dey + bpl teor11 + + ldx #6 ;(zp,x) + ldy #3 +teor12 + set_ay absEOa,0 + eor (indEO,x) + tst_ay absrlo,absflo,0 + dex + dex + dey + bpl teor12 + ldx #6 + ldy #3 +teor13 + set_ay absEOa,$ff + eor (indEO,x) + tst_ay absrlo,absflo,$ff-fnz + dex + dex + dey + bpl teor13 + + ldy #3 ;(zp),y +teor14 + set_ay absEOa,0 + eor (indEO),y + tst_ay absrlo,absflo,0 + dey + bpl teor14 + ldy #3 +teor15 + set_ay absEOa,$ff + eor (indEO),y + tst_ay absrlo,absflo,$ff-fnz + dey + bpl teor15 + next_test + +; OR + ldx #3 ;immediate - self modifying code +tora lda zpOR,x + sta ex_orai+1 ;set ORA # operand + set_ax absORa,0 + jsr ex_orai ;execute ORA # in RAM + tst_ax absrlo,absflo,0 + dex + bpl tora + ldx #3 +tora1 lda zpOR,x + sta ex_orai+1 ;set ORA # operand + set_ax absORa,$ff + jsr ex_orai ;execute ORA # in RAM + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tora1 + + ldx #3 ;zp +tora2 lda zpOR,x + sta zpt + set_ax absORa,0 + ora zpt + tst_ax absrlo,absflo,0 + dex + bpl tora2 + ldx #3 +tora3 lda zpOR,x + sta zpt + set_ax absORa,$ff + ora zpt + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tora3 + + ldx #3 ;abs +tora4 lda zpOR,x + sta abst + set_ax absORa,0 + ora abst + tst_ax absrlo,absflo,0 + dex + bpl tora4 + ldx #3 +tora5 lda zpOR,x + sta abst + set_ax absORa,$ff + ora abst + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tora6 + + ldx #3 ;zp,x +tora6 + set_ax absORa,0 + ora zpOR,x + tst_ax absrlo,absflo,0 + dex + bpl tora6 + ldx #3 +tora7 + set_ax absORa,$ff + ora zpOR,x + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tora7 + + ldx #3 ;abs,x +tora8 + set_ax absORa,0 + ora absOR,x + tst_ax absrlo,absflo,0 + dex + bpl tora8 + ldx #3 +tora9 + set_ax absORa,$ff + ora absOR,x + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tora9 + + ldy #3 ;abs,y +tora10 + set_ay absORa,0 + ora absOR,y + tst_ay absrlo,absflo,0 + dey + bpl tora10 + ldy #3 +tora11 + set_ay absORa,$ff + ora absOR,y + tst_ay absrlo,absflo,$ff-fnz + dey + bpl tora11 + + ldx #6 ;(zp,x) + ldy #3 +tora12 + set_ay absORa,0 + ora (indOR,x) + tst_ay absrlo,absflo,0 + dex + dex + dey + bpl tora12 + ldx #6 + ldy #3 +tora13 + set_ay absORa,$ff + ora (indOR,x) + tst_ay absrlo,absflo,$ff-fnz + dex + dex + dey + bpl tora13 + + ldy #3 ;(zp),y +tora14 + set_ay absORa,0 + ora (indOR),y + tst_ay absrlo,absflo,0 + dey + bpl tora14 + ldy #3 +tora15 + set_ay absORa,$ff + ora (indOR),y + tst_ay absrlo,absflo,$ff-fnz + dey + bpl tora15 + if I_flag = 3 + cli + endif + next_test + +; full binary add/subtract test +; iterates through all combinations of operands and carry input +; uses increments/decrements to predict result & result flags + cld + ldx #ad2 ;for indexed test + ldy #$ff ;max range + lda #0 ;start with adding zeroes & no carry + sta adfc ;carry in - for diag + sta ad1 ;operand 1 - accumulator + sta ad2 ;operand 2 - memory or immediate + sta ada2 ;non zp + sta adrl ;expected result bits 0-7 + sta adrh ;expected result bit 8 (carry out) + lda #$ff ;complemented operand 2 for subtract + sta sb2 + sta sba2 ;non zp + lda #2 ;expected Z-flag + sta adrf +tadd clc ;test with carry clear + jsr chkadd + inc adfc ;now with carry + inc adrl ;result +1 + php ;save N & Z from low result + php + pla ;accu holds expected flags + and #$82 ;mask N & Z + plp + bne tadd1 + inc adrh ;result bit 8 - carry +tadd1 ora adrh ;merge C to expected flags + sta adrf ;save expected flags except overflow + sec ;test with carry set + jsr chkadd + dec adfc ;same for operand +1 but no carry + inc ad1 + bne tadd ;iterate op1 + lda #0 ;preset result to op2 when op1 = 0 + sta adrh + inc ada2 + inc ad2 + php ;save NZ as operand 2 becomes the new result + pla + and #$82 ;mask N00000Z0 + sta adrf ;no need to check carry as we are adding to 0 + dec sb2 ;complement subtract operand 2 + dec sba2 + lda ad2 + sta adrl + bne tadd ;iterate op2 + if disable_decimal < 1 + next_test + +; decimal add/subtract test +; *** WARNING - tests documented behavior only! *** +; only valid BCD operands are tested, N V Z flags are ignored +; iterates through all valid combinations of operands and carry input +; uses increments/decrements to predict result & carry flag + sed + ldx #ad2 ;for indexed test + ldy #$ff ;max range + lda #$99 ;start with adding 99 to 99 with carry + sta ad1 ;operand 1 - accumulator + sta ad2 ;operand 2 - memory or immediate + sta ada2 ;non zp + sta adrl ;expected result bits 0-7 + lda #1 ;set carry in & out + sta adfc ;carry in - for diag + sta adrh ;expected result bit 8 (carry out) + lda #0 ;complemented operand 2 for subtract + sta sb2 + sta sba2 ;non zp +tdad sec ;test with carry set + jsr chkdad + dec adfc ;now with carry clear + lda adrl ;decimal adjust result + bne tdad1 ;skip clear carry & preset result 99 (9A-1) + dec adrh + lda #$99 + sta adrl + bne tdad3 +tdad1 and #$f ;lower nibble mask + bne tdad2 ;no decimal adjust needed + dec adrl ;decimal adjust (?0-6) + dec adrl + dec adrl + dec adrl + dec adrl + dec adrl +tdad2 dec adrl ;result -1 +tdad3 clc ;test with carry clear + jsr chkdad + inc adfc ;same for operand -1 but with carry + lda ad1 ;decimal adjust operand 1 + beq tdad5 ;iterate operand 2 + and #$f ;lower nibble mask + bne tdad4 ;skip decimal adjust + dec ad1 ;decimal adjust (?0-6) + dec ad1 + dec ad1 + dec ad1 + dec ad1 + dec ad1 +tdad4 dec ad1 ;operand 1 -1 + jmp tdad ;iterate op1 + +tdad5 lda #$99 ;precharge op1 max + sta ad1 + lda ad2 ;decimal adjust operand 2 + beq tdad7 ;end of iteration + and #$f ;lower nibble mask + bne tdad6 ;skip decimal adjust + dec ad2 ;decimal adjust (?0-6) + dec ad2 + dec ad2 + dec ad2 + dec ad2 + dec ad2 + inc sb2 ;complemented decimal adjust for subtract (?9+6) + inc sb2 + inc sb2 + inc sb2 + inc sb2 + inc sb2 +tdad6 dec ad2 ;operand 2 -1 + inc sb2 ;complemented operand for subtract + lda sb2 + sta sba2 ;copy as non zp operand + lda ad2 + sta ada2 ;copy as non zp operand + sta adrl ;new result since op1+carry=00+carry +op2=op2 + inc adrh ;result carry + bne tdad ;iterate op2 +tdad7 + next_test + +; decimal/binary switch test +; tests CLD, SED, PLP, RTI to properly switch between decimal & binary opcode +; tables + clc + cld + php + lda #$55 + adc #$55 + cmp #$aa + trap_ne ;expected binary result after cld + clc + sed + php + lda #$55 + adc #$55 + cmp #$10 + trap_ne ;expected decimal result after sed + cld + plp + lda #$55 + adc #$55 + cmp #$10 + trap_ne ;expected decimal result after plp D=1 + plp + lda #$55 + adc #$55 + cmp #$aa + trap_ne ;expected binary result after plp D=0 + clc + lda #hi bin_rti_ret ;emulated interrupt for rti + pha + lda #lo bin_rti_ret + pha + php + sed + lda #hi dec_rti_ret ;emulated interrupt for rti + pha + lda #lo dec_rti_ret + pha + php + cld + rti +dec_rti_ret + lda #$55 + adc #$55 + cmp #$10 + trap_ne ;expected decimal result after rti D=1 + rti +bin_rti_ret + lda #$55 + adc #$55 + cmp #$aa + trap_ne ;expected binary result after rti D=0 + endif + + lda test_case + cmp #test_num + trap_ne ;previous test is out of sequence + lda #$f0 ;mark opcode testing complete + sta test_case + +; final RAM integrity test +; verifies that none of the previous tests has altered RAM outside of the +; designated write areas. + check_ram +; *** DEBUG INFO *** +; to debug checksum errors uncomment check_ram in the next_test macro to +; narrow down the responsible opcode. +; may give false errors when monitor, OS or other background activity is +; allowed during previous tests. + + +; S U C C E S S ************************************************ +; ------------- + success ;if you get here everything went well +; ------------- +; S U C C E S S ************************************************ + jmp start ;run again + + if disable_decimal < 1 +; core subroutine of the decimal add/subtract test +; *** WARNING - tests documented behavior only! *** +; only valid BCD operands are tested, N V Z flags are ignored +; iterates through all valid combinations of operands and carry input +; uses increments/decrements to predict result & carry flag +chkdad +; decimal ADC / SBC zp + php ;save carry for subtract + lda ad1 + adc ad2 ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda ad1 + sbc sb2 ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad flags + plp +; decimal ADC / SBC abs + php ;save carry for subtract + lda ad1 + adc ada2 ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda ad1 + sbc sba2 ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp +; decimal ADC / SBC # + php ;save carry for subtract + lda ad2 + sta ex_adci+1 ;set ADC # operand + lda ad1 + jsr ex_adci ;execute ADC # in RAM + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda sb2 + sta ex_sbci+1 ;set SBC # operand + lda ad1 + jsr ex_sbci ;execute SBC # in RAM + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp +; decimal ADC / SBC zp,x + php ;save carry for subtract + lda ad1 + adc 0,x ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda ad1 + sbc sb2-ad2,x ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp +; decimal ADC / SBC abs,x + php ;save carry for subtract + lda ad1 + adc ada2-ad2,x ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda ad1 + sbc sba2-ad2,x ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp +; decimal ADC / SBC abs,y + php ;save carry for subtract + lda ad1 + adc ada2-$ff,y ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda ad1 + sbc sba2-$ff,y ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp +; decimal ADC / SBC (zp,x) + php ;save carry for subtract + lda ad1 + adc (lo adi2-ad2,x) ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda ad1 + sbc (lo sbi2-ad2,x) ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp +; decimal ADC / SBC (abs),y + php ;save carry for subtract + lda ad1 + adc (adiy2),y ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda ad1 + sbc (sbiy2),y ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + rts + endif + +; core subroutine of the full binary add/subtract test +; iterates through all combinations of operands and carry input +; uses increments/decrements to predict result & result flags +chkadd lda adrf ;add V-flag if overflow + and #$83 ;keep N-----ZC / clear V + pha + lda ad1 ;test sign unequal between operands + eor ad2 + bmi ckad1 ;no overflow possible - operands have different sign + lda ad1 ;test sign equal between operands and result + eor adrl + bpl ckad1 ;no overflow occured - operand and result have same sign + pla + ora #$40 ;set V + pha +ckad1 pla + sta adrf ;save expected flags +; binary ADC / SBC zp + php ;save carry for subtract + lda ad1 + adc ad2 ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sb2 ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp +; binary ADC / SBC abs + php ;save carry for subtract + lda ad1 + adc ada2 ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sba2 ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp +; binary ADC / SBC # + php ;save carry for subtract + lda ad2 + sta ex_adci+1 ;set ADC # operand + lda ad1 + jsr ex_adci ;execute ADC # in RAM + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda sb2 + sta ex_sbci+1 ;set SBC # operand + lda ad1 + jsr ex_sbci ;execute SBC # in RAM + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp +; binary ADC / SBC zp,x + php ;save carry for subtract + lda ad1 + adc 0,x ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sb2-ad2,x ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp +; binary ADC / SBC abs,x + php ;save carry for subtract + lda ad1 + adc ada2-ad2,x ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sba2-ad2,x ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp +; binary ADC / SBC abs,y + php ;save carry for subtract + lda ad1 + adc ada2-$ff,y ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sba2-$ff,y ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp +; binary ADC / SBC (zp,x) + php ;save carry for subtract + lda ad1 + adc (lo adi2-ad2,x) ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc (lo sbi2-ad2,x) ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp +; binary ADC / SBC (abs),y + php ;save carry for subtract + lda ad1 + adc (adiy2),y ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc (sbiy2),y ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + rts + +; target for the jump absolute test + dey + dey +test_far + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_cs ;flags loaded? + trap_vs + trap_mi + trap_eq + cmp #'F' ;registers loaded? + trap_ne + cpx #'A' + trap_ne + cpy #('R'-3) + trap_ne + pha ;save a,x + txa + pha + tsx + cpx #$fd ;check SP + trap_ne + pla ;restore x + tax + set_stat $ff + pla ;restore a + inx ;return registers with modifications + eor #$aa ;N=1, V=1, Z=0, C=1 + jmp far_ret + +; target for the jump indirect test + align +ptr_tst_ind dw test_ind +ptr_ind_ret dw ind_ret + trap ;runover protection + dey + dey +test_ind + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_cs ;flags loaded? + trap_vs + trap_mi + trap_eq + cmp #'I' ;registers loaded? + trap_ne + cpx #'N' + trap_ne + cpy #('D'-3) + trap_ne + pha ;save a,x + txa + pha + tsx + cpx #$fd ;check SP + trap_ne + pla ;restore x + tax + set_stat $ff + pla ;restore a + inx ;return registers with modifications + eor #$aa ;N=1, V=1, Z=0, C=1 + jmp (ptr_ind_ret) + trap ;runover protection + jmp start ;catastrophic error - cannot continue + +; target for the jump subroutine test + dey + dey +test_jsr + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_cs ;flags loaded? + trap_vs + trap_mi + trap_eq + cmp #'J' ;registers loaded? + trap_ne + cpx #'S' + trap_ne + cpy #('R'-3) + trap_ne + pha ;save a,x + txa + pha + tsx ;sp -4? (return addr,a,x) + cpx #$fb + trap_ne + lda $1ff ;propper return on stack + cmp #hi(jsr_ret) + trap_ne + lda $1fe + cmp #lo(jsr_ret) + trap_ne + set_stat $ff + pla ;pull x,a + tax + pla + inx ;return registers with modifications + eor #$aa ;N=1, V=1, Z=0, C=1 + rts + trap ;runover protection + jmp start ;catastrophic error - cannot continue + +;trap in case of unexpected IRQ, NMI, BRK, RESET - BRK test target +nmi_trap + trap ;check stack for conditions at NMI + jmp start ;catastrophic error - cannot continue +res_trap + trap ;unexpected RESET + jmp start ;catastrophic error - cannot continue + + dey + dey +irq_trap ;BRK test or unextpected BRK or IRQ + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + ;next traps could be caused by unexpected BRK or IRQ + ;check stack for BREAK and originating location + ;possible jump/branch into weeds (uninitialized space) + cmp #$ff-'B' ;BRK pass 2 registers loaded? + beq break2 + cmp #'B' ;BRK pass 1 registers loaded? + trap_ne + cpx #'R' + trap_ne + cpy #'K'-3 + trap_ne + sta irq_a ;save registers during break test + stx irq_x + tsx ;test break on stack + lda $102,x + cmp_flag 0 ;break test should have B=1 & unused=1 on stack + trap_ne ; - no break flag on stack + pla + cmp_flag intdis ;should have added interrupt disable + trap_ne + tsx + cpx #$fc ;sp -3? (return addr, flags) + trap_ne + lda $1ff ;propper return on stack + cmp #hi(brk_ret0) + trap_ne + lda $1fe + cmp #lo(brk_ret0) + trap_ne + load_flag $ff + pha + ldx irq_x + inx ;return registers with modifications + lda irq_a + eor #$aa + plp ;N=1, V=1, Z=1, C=1 but original flags should be restored + rti + trap ;runover protection + jmp start ;catastrophic error - cannot continue + +break2 ;BRK pass 2 + cpx #$ff-'R' + trap_ne + cpy #$ff-'K'-3 + trap_ne + sta irq_a ;save registers during break test + stx irq_x + tsx ;test break on stack + lda $102,x + cmp_flag $ff ;break test should have B=1 + trap_ne ; - no break flag on stack + pla + ora #decmode ;ignore decmode cleared if 65c02 + cmp_flag $ff ;actual passed flags + trap_ne + tsx + cpx #$fc ;sp -3? (return addr, flags) + trap_ne + lda $1ff ;propper return on stack + cmp #hi(brk_ret1) + trap_ne + lda $1fe + cmp #lo(brk_ret1) + trap_ne + load_flag intdis + pha + ldx irq_x + inx ;return registers with modifications + lda irq_a + eor #$aa + plp ;N=0, V=0, Z=0, C=0 but original flags should be restored + rti + trap ;runover protection + jmp start ;catastrophic error - cannot continue + + if report = 1 + include "report.i65" + endif + +;copy of data to initialize BSS segment + if load_data_direct != 1 +zp_init +zps_ db $80,1 ;additional shift pattern to test zero result & flag +zp1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +zp7f_ db $7f ;test pattern for compare +;logical zeropage operands +zpOR_ db 0,$1f,$71,$80 ;test pattern for OR +zpAN_ db $0f,$ff,$7f,$80 ;test pattern for AND +zpEO_ db $ff,$0f,$8f,$8f ;test pattern for EOR +;indirect addressing pointers +ind1_ dw abs1 ;indirect pointer to pattern in absolute memory + dw abs1+1 + dw abs1+2 + dw abs1+3 + dw abs7f +inw1_ dw abs1-$f8 ;indirect pointer for wrap-test pattern +indt_ dw abst ;indirect pointer to store area in absolute memory + dw abst+1 + dw abst+2 + dw abst+3 +inwt_ dw abst-$f8 ;indirect pointer for wrap-test store +indAN_ dw absAN ;indirect pointer to AND pattern in absolute memory + dw absAN+1 + dw absAN+2 + dw absAN+3 +indEO_ dw absEO ;indirect pointer to EOR pattern in absolute memory + dw absEO+1 + dw absEO+2 + dw absEO+3 +indOR_ dw absOR ;indirect pointer to OR pattern in absolute memory + dw absOR+1 + dw absOR+2 + dw absOR+3 +;add/subtract indirect pointers +adi2_ dw ada2 ;indirect pointer to operand 2 in absolute memory +sbi2_ dw sba2 ;indirect pointer to complemented operand 2 (SBC) +adiy2_ dw ada2-$ff ;with offset for indirect indexed +sbiy2_ dw sba2-$ff +zp_end + if (zp_end - zp_init) != (zp_bss_end - zp_bss) + ;force assembler error if size is different + ERROR ERROR ERROR ;mismatch between bss and zeropage data + endif +data_init +ex_and_ and #0 ;execute immediate opcodes + rts +ex_eor_ eor #0 ;execute immediate opcodes + rts +ex_ora_ ora #0 ;execute immediate opcodes + rts +ex_adc_ adc #0 ;execute immediate opcodes + rts +ex_sbc_ sbc #0 ;execute immediate opcodes + rts +;zps db $80,1 ;additional shift patterns test zero result & flag +abs1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +abs7f_ db $7f ;test pattern for compare +;loads +fLDx_ db fn,fn,0,fz ;expected flags for load +;shifts +rASL_ ;expected result ASL & ROL -carry +rROL_ db 0,2,$86,$04,$82,0 +rROLc_ db 1,3,$87,$05,$83,1 ;expected result ROL +carry +rLSR_ ;expected result LSR & ROR -carry +rROR_ db $40,0,$61,$41,$20,0 +rRORc_ db $c0,$80,$e1,$c1,$a0,$80 ;expected result ROR +carry +fASL_ ;expected flags for shifts +fROL_ db fzc,0,fnc,fc,fn,fz ;no carry in +fROLc_ db fc,0,fnc,fc,fn,0 ;carry in +fLSR_ +fROR_ db 0,fzc,fc,0,fc,fz ;no carry in +fRORc_ db fn,fnc,fnc,fn,fnc,fn ;carry in +;increments (decrements) +rINC_ db $7f,$80,$ff,0,1 ;expected result for INC/DEC +fINC_ db 0,fn,fn,fz,0 ;expected flags for INC/DEC +;logical memory operand +absOR_ db 0,$1f,$71,$80 ;test pattern for OR +absAN_ db $0f,$ff,$7f,$80 ;test pattern for AND +absEO_ db $ff,$0f,$8f,$8f ;test pattern for EOR +;logical accu operand +absORa_ db 0,$f1,$1f,0 ;test pattern for OR +absANa_ db $f0,$ff,$ff,$ff ;test pattern for AND +absEOa_ db $ff,$f0,$f0,$0f ;test pattern for EOR +;logical results +absrlo_ db 0,$ff,$7f,$80 +absflo_ db fz,fn,0,fn +data_end + if (data_end - data_init) != (data_bss_end - data_bss) + ;force assembler error if size is different + ERROR ERROR ERROR ;mismatch between bss and data + endif + +vec_init + dw nmi_trap + dw res_trap + dw irq_trap +vec_bss equ $fffa + endif ;end of RAM init data + + if (load_data_direct = 1) & (ROM_vectors = 1) + org $fffa ;vectors + dw nmi_trap + dw res_trap + dw irq_trap + endif + + end start + \ No newline at end of file diff --git a/runtime.ts b/runtime.ts index 1527c62..6bf9892 100644 --- a/runtime.ts +++ b/runtime.ts @@ -23,6 +23,7 @@ await cpu.loadInstructions() const args = parseArgs(Deno.args) const binStart = parseInt(args.b ?? args.binStart ?? '8000', 16) +const resVec = parseInt(args.s ?? args.start ?? binStart.toString(16), 16) if (Number.isNaN(binStart)) throw 'binStart is NaN!' @@ -30,19 +31,20 @@ if (Number.isNaN(binStart)) // read code from file const code = Deno.readFileSync(args._.toString() || 'msbasic/tmp/eater.bin') -// mem address $0000 -ram[0xFFFC] = binStart & 0x00FF -ram[0xFFFD] = (binStart & 0xFF00) >> 8 - // write code to ram before execution for (let offset = 0; offset < code.length; offset++) { const byte = code[offset]; ram[binStart + offset] = byte; } +// mem address $0000 +ram[0xFFFC] = resVec & 0x00FF +ram[0xFFFD] = (resVec & 0xFF00) >> 8 + // pull RESB low to reset the 65c02 cpu.io.reset.LO() cpu.cycle() +// cpu.programCounter.set(0x13) //the cpu reset, pull RESB high and start execution! cpu.io.reset.HI() @@ -71,6 +73,7 @@ const debug = Deno.args.includes('-d') let skip = 0; let breakpoints: number[] = [] let instBreakpoints: string[] = [] +let memBreakpoints: number[] = [] if (debug) { console.info('NOTE; the instructions are executed after input') @@ -87,6 +90,12 @@ while (!cpu.io.interruptRequest.high) { console.log('uh', instId, 'unknown') break; } + let addr: number | undefined; + if (goog.mode != 'implied' && goog.mode != 'implicit') { + const pastPC = cpu.programCounter.num() + addr = cpu.getAddr(goog.mode); + cpu.programCounter.set(pastPC) + } const instr = goog; if (debug) console.debug(cpu.programCounter.num().toString(16).padStart(4, '0'),instr.mnemonic, instr.mode) @@ -103,6 +112,11 @@ while (!cpu.io.interruptRequest.high) { skip = 0; console.log('hit breakpoint on', cpu.programCounter.num().toString(16)) } + if (addr && memBreakpoints.includes(addr)) { + memBreakpoints = memBreakpoints.filter(k => k != addr) + skip = 0; + console.log('hit breakpoint on', addr.toString(16)) + } if (skip != 0) { skip-- break dbg; @@ -191,8 +205,17 @@ I[INS] - breakpoint instruction`); ram[0x5000] = num; ram[0x5001] = 0x08; console.log(`set $5000 to 0x${num.toString(16).padStart(2, '0')} and $5001 to 08`) - console.log('skipping 8 cycles'); - skip = 8; + console.log(`set breakpoint to accessing address 5000`) + memBreakpoints.push(0x5000) + } else if (i[0] == 'm'.charCodeAt(0)) { + const num = parseInt(new TextDecoder().decode(i.slice(1, 7)).replace('\n', '').replaceAll('\0', ''), 16); + if (Number.isNaN(num)) { + console.log('NaN') + break dbg; + } + console.log(`set breakpoint to accessing address`, num.toString(16)) + memBreakpoints.push(num) + continue; } break; } diff --git a/thing.s b/thing.s index 115f596..5e03ad8 100644 --- a/thing.s +++ b/thing.s @@ -6,6 +6,8 @@ ACIA_CTRL = $5003 _start: lda #$64 jsr CHROUT + lda #$20 + pha BRK CHROUT: |